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Results 1 - 10 of 10 for SLL (0.02 sec)

  1. src/internal/runtime/atomic/atomic_mipsx.s

    	MOVBU	val+4(FP), R2
    	MOVW	$~3, R3
    	AND	R1, R3
    #ifdef GOARCH_mips
    	// Big endian.  ptr = ptr ^ 3
    	XOR	$3, R1
    #endif
    	AND	$3, R1, R4	// R4 = ((ptr & 3) * 8)
    	SLL	$3, R4
    	MOVW	$0xFF, R5
    	SLL	R4, R2
    	SLL	R4, R5
    	NOR	R0, R5
    	OR	R5, R2	// Shift val for aligned ptr. R2 = val << R4 | ^(0xFF << R4)
    	SYNC
    try_and8:
    	LL	(R3), R4	// R4 = *R3
    	AND	R2, R4
    	SC	R4, (R3)	// *R3 = R4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 21:29:34 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  2. src/crypto/sha512/sha512block_riscv64.s

    	MOVBU	((index*8)+3)(X29), X8; \
    	SLL	$56, X5; \
    	SLL	$48, X6; \
    	OR	X5, X6, X5; \
    	SLL	$40, X7; \
    	OR	X5, X7, X5; \
    	SLL	$32, X8; \
    	OR	X5, X8, X5; \
    	MOVBU	((index*8)+4)(X29), X9; \
    	MOVBU	((index*8)+5)(X29), X6; \
    	MOVBU	((index*8)+6)(X29), X7; \
    	MOVBU	((index*8)+7)(X29), X8; \
    	SLL	$24, X9; \
    	OR	X5, X9, X5; \
    	SLL	$16, X6; \
    	OR	X5, X6, X5; \
    	SLL	$8, X7; \
    	OR	X5, X7, X5; \
    	OR	X5, X8, X5; \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 9.1K bytes
    - Viewed (0)
  3. test/codegen/rotate.go

    	z &= 15
    
    	// amd64:"ROLW",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x<<z | x>>(16-z)
    
    	// amd64:"RORW",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x>>z | x<<(16-z)
    
    	return a
    }
    
    func rot8nc(x uint8, z uint) uint8 {
    	var a uint8
    
    	z &= 7
    
    	// amd64:"ROLB",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x<<z | x>>(8-z)
    
    	// amd64:"RORB",-"ANDQ"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	SUB	R4, R5			// a5101100
    	SUBV	R4, R5			// a5901100
    	ADD	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/mips.s

    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	SLL	R1, R2, R3
    
    	//	LSHW rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	SLL	R1, R2
    
    	//	LSHW imm ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	SLL	$4, R1, R2
    
    	//	LSHW imm ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	SLL	$4, R1
    
    	//
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  6. src/internal/runtime/atomic/atomic_riscv64.s

    	MOV	ptr+0(FP), A0
    	MOVBU	val+8(FP), A1
    	AND	$3, A0, A2
    	AND	$-4, A0
    	SLL	$3, A2
    	XOR	$255, A1
    	SLL	A2, A1
    	XOR	$-1, A1
    	AMOANDW A1, (A0), ZERO
    	RET
    
    // func Or8(ptr *uint8, val uint8)
    TEXT ·Or8(SB), NOSPLIT, $0-9
    	MOV	ptr+0(FP), A0
    	MOVBU	val+8(FP), A1
    	AND	$3, A0, A2
    	AND	$-4, A0
    	SLL	$3, A2
    	SLL	A2, A1
    	AMOORW	A1, (A0), ZERO
    	RET
    
    // func And(ptr *uint32, val uint32)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 7K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/arm/anames.go

    	"FMULAD",
    	"FNMULAF",
    	"FNMULAD",
    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/mips/anames.go

    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"ROTR",
    	"ROTRV",
    	"SC",
    	"SCV",
    	"SEB",
    	"SEH",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"SYNC",
    	"SYSCALL",
    	"TEQ",
    	"TLBP",
    	"TLBR",
    	"TLBWI",
    	"TLBWR",
    	"TNE",
    	"WORD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/loong64/anames.go

    	"MULF",
    	"MULU",
    	"MULH",
    	"MULHU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"SC",
    	"SCV",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"ROTR",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/riscv/anames.go

    	obj.A_ARCHSPECIFIC: "ADDI",
    	"SLTI",
    	"SLTIU",
    	"ANDI",
    	"ORI",
    	"XORI",
    	"SLLI",
    	"SRLI",
    	"SRAI",
    	"LUI",
    	"AUIPC",
    	"ADD",
    	"SLT",
    	"SLTU",
    	"AND",
    	"OR",
    	"XOR",
    	"SLL",
    	"SRL",
    	"SUB",
    	"SRA",
    	"JAL",
    	"JALR",
    	"BEQ",
    	"BNE",
    	"BLT",
    	"BLTU",
    	"BGE",
    	"BGEU",
    	"LW",
    	"LWU",
    	"LH",
    	"LHU",
    	"LB",
    	"LBU",
    	"SW",
    	"SH",
    	"SB",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
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