Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 9 of 9 for ROTRV (0.04 sec)

  1. test/codegen/rotate.go

    func rot64(x uint64) uint64 {
    	var a uint64
    
    	// amd64:"ROLQ\t[$]7"
    	// ppc64x:"ROTL\t[$]7"
    	// loong64: "ROTRV\t[$]57"
    	// riscv64: "RORI\t[$]57"
    	a += x<<7 | x>>57
    
    	// amd64:"ROLQ\t[$]8"
    	// arm64:"ROR\t[$]56"
    	// s390x:"RISBGZ\t[$]0, [$]63, [$]8, "
    	// ppc64x:"ROTL\t[$]8"
    	// loong64: "ROTRV\t[$]56"
    	// riscv64: "RORI\t[$]56"
    	a += x<<8 + x>>56
    
    	// amd64:"ROLQ\t[$]9"
    	// arm64:"ROR\t[$]55"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 6K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    	SLLV	R4, R5			// a5901800
    	SLLV	R4, R5, R6		// a6901800
    	ROTRV	R4, R5			// a5901b00
    	ROTRV	R4, R5, R6		// a6901b00
    	CLO	R4, R5			// 85100000
    	CLZ	R4, R5			// 85140000
    	ADDF	F4, F5			// a5900001
    	ADDF	F4, R5, F6		// a6900001
    	CMPEQF	F4, R5			// a010120c
    	ABSF	F4, F5			// 85041401
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/mips/anames.go

    	"MOVWL",
    	"MOVWR",
    	"MSUB",
    	"MUL",
    	"MULD",
    	"MULF",
    	"MULU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"ROTR",
    	"ROTRV",
    	"SC",
    	"SCV",
    	"SEB",
    	"SEH",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"SYNC",
    	"SYSCALL",
    	"TEQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/loong64/anames.go

    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    	"MOVV",
    	"MOVVL",
    	"MOVVR",
    	"SLLV",
    	"SRAV",
    	"SRLV",
    	"ROTRV",
    	"DIVV",
    	"DIVVU",
    	"REMV",
    	"REMVU",
    	"MULV",
    	"MULVU",
    	"MULHV",
    	"MULHVU",
    	"ADDV",
    	"ADDVU",
    	"SUBV",
    	"SUBVU",
    	"TRUNCFV",
    	"TRUNCDV",
    	"TRUNCFW",
    	"TRUNCDW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/mips64.s

    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    	SRLV	R27, R6   	// 03663016
    	SRA	R11, R19	// 01739807
    	SRAV	R20, R19	// 02939817
    	ROTR	R20, R19	// 02939846
    	ROTRV	R16, R9		// 02094856
    
    //	LSHW imm ',' sreg ',' rreg
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"},                    // arg0 right rotate by (arg1 mod 64) bits
    		{name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64"},   // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
    (RotateLeft32 x y) => (ROTR  x (NEGV <y.Type> y))
    (RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y))
    
    // unary ops
    (Neg(64|32|16|8) ...) => (NEGV ...)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
    
    (Sqrt ...) => (SQRTD ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		v.AuxInt = int64ToAuxInt(c & 31)
    		v.AddArg(x)
    		return true
    	}
    	return false
    }
    func rewriteValueLOONG64_OpLOONG64ROTRV(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROTRV x (MOVVconst [c]))
    	// result: (ROTRVconst x [c&63])
    	for {
    		x := v_0
    		if v_1.Op != OpLOONG64MOVVconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpLOONG64ROTRVconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
    			},
    		},
    	},
    	{
    		name:   "ROTRV",
    		argLen: 2,
    		asm:    loong64.AROTRV,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
Back to top