REMU - Code Search

src/cmd/internal/obj/mips/anames.go

	"MOVW",
	"MOVWD",
	"MOVWF",
	"MOVWL",
	"MOVWR",
	"MSUB",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"ROTR",
	"ROTRV",
	"SC",
	"SCV",
	"SEB",
	"SEH",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue Aug 08 12:17:12 UTC 2023

- 1.4K bytes

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github.com/golang/go

src/cmd/internal/obj/loong64/anames.go

	"MOVWF",
	"MOVWL",
	"MOVWR",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULH",
	"MULHU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"SC",
	"SCV",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"ROTR",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",
	"DBAR",
	"SYSCALL",
	"TEQ",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 02:04:54 UTC 2024

- 1.9K bytes

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github.com/golang/go

src/cmd/internal/obj/riscv/anames.go

	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",
	"AMOORD",
	"AMOXORD",
	"AMOMAXD",
	"AMOMAXUD",
	"AMOMIND",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed Mar 20 14:19:33 UTC 2024

- 2.9K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/loong64enc1.s

	MULH	R4, R5	   		// a5901c00
	MULH	R4, R5, R6	   	// a6901c00
	MULHU	R4, R5			// a5101d00
	MULHU	R4, R5, R6		// a6101d00
	REM	R4, R5	  		// a5902000
	REM	R4, R5, R6	  	// a6902000
	REMU	R4, R5	   		// a5902100
	REMU	R4, R5, R6	   	// a6902100
	DIV	R4, R5	  		// a5102000
	DIV	R4, R5, R6	  	// a6102000
	DIVU	R4, R5	   		// a5102100
	DIVU	R4, R5, R6	   	// a6102100
	SRLV	R4, R5 			// a5101900

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 02:04:54 UTC 2024

- 8.2K bytes

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github.com/golang/go

src/cmd/internal/obj/ppc64/anames.go

	"MULLWVCC",
	"MULLWV",
	"NAND",
	"NANDCC",
	"NEG",
	"NEGCC",
	"NEGVCC",
	"NEGV",
	"NOR",
	"NORCC",
	"OR",
	"ORCC",
	"ORN",
	"ORNCC",
	"ORIS",
	"REM",
	"REMU",
	"RFI",
	"RLWMI",
	"RLWMICC",
	"RLWNM",
	"RLWNMCC",
	"CLRLSLWI",
	"SLW",
	"SLWCC",
	"SRW",
	"SRAW",
	"SRAWCC",
	"SRWCC",
	"STBCCC",
	"STHCCC",
	"STSW",
	"STWCCC",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Mon Apr 01 18:50:29 UTC 2024

- 6.7K bytes

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

		{name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"},
		{name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1
		{name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64"},
		{name: "REMW", argLength: 2, reg: gp21, asm: "REMW", typ: "Int32"},
		{name: "REMUW", argLength: 2, reg: gp21, asm: "REMUW", typ: "UInt32"},

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 07 14:57:07 UTC 2024

- 30.7K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/mips64.s

	DIVU	R14, R9		// 012e001b
	DIVV	R8, R13		// 01a8001e
	DIVVU	R16, R19	// 0270001f

//	LREM rreg ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	REM	R18, R22	// 02d2001a
	REMU	R14, R9		// 012e001b
	REMV	R8, R13		// 01a8001e
	REMVU	R16, R19	// 0270001f

//	LSHW rreg ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SLL	R1, R2, R3	// 00221804

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue Aug 08 12:17:12 UTC 2023

- 12.4K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/riscv64.s

	MULHU	X5, X6, X7				// b3335302
	MULHSU	X5, X6, X7				// b3235302
	MULW	X5, X6, X7				// bb035302
	DIV	X5, X6, X7				// b3435302
	DIVU	X5, X6, X7				// b3535302
	REM	X5, X6, X7				// b3635302
	REMU	X5, X6, X7				// b3735302
	DIVW	X5, X6, X7				// bb435302
	DIVUW	X5, X6, X7				// bb535302
	REMW	X5, X6, X7				// bb635302
	REMUW	X5, X6, X7				// bb735302

	// 8.2: Load-Reserved/Store-Conditional

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri Mar 22 04:42:21 UTC 2024

- 16.7K bytes

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/RISCV64.rules

// (x + y) / 2 => (x / 2) + (y / 2) + (x & y & 1)
(Avg64u <t> x y) => (ADD (ADD <t> (SRLI <t> [1] x) (SRLI <t> [1] y)) (ANDI <t> [1] (AND <t> x y)))

(Mod64 x y [false])  => (REM x y)
(Mod64u ...) => (REMU  ...)
(Mod32 x y [false])  => (REMW x y)
(Mod32u ...) => (REMUW ...)
(Mod16 x y [false])  => (REMW  (SignExt16to32 x) (SignExt16to32 y))
(Mod16u x y) => (REMUW (ZeroExt16to32 x) (ZeroExt16to32 y))

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 07 14:57:07 UTC 2024

- 40.3K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/ppc64.s

	DIVDECC R3, R4, R5              // 7ca41b53
	DIVDEU R3, R4, R5               // 7ca41b12
	DIVDEUCC R3, R4, R5             // 7ca41b13

	REM R3, R4, R5                  // 7fe41bd67fff19d67cbf2050
	REMU R3, R4, R5                 // 7fe41b967fff19d67bff00287cbf2050
	REMD R3, R4, R5                 // 7fe41bd27fff19d27cbf2050
	REMDU R3, R4, R5                // 7fe41b927fff19d27cbf2050

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri May 17 21:53:50 UTC 2024

- 50.2K bytes

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