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Results 1 - 10 of 32 for SGTU (0.13 sec)
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src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Round(32|64)F ...) => (Copy ...) // comparisons (Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y)) (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y)) (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/internal/bytealg/compare_mipsx.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Round(32|64)F ...) => (Copy ...) // comparisons (Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y)) (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y)) (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/runtime/memclr_mips64x.s
ADDV R1, R2, R4 // if less than 16 bytes or no MSA, do words check SGTU $16, R2, R3 BNE R3, no_msa MOVBU internal∕cpu·MIPS64X+const_offsetMIPS64XHasMSA(SB), R3 BEQ R3, R0, no_msa VMOVB $0, W0 SGTU $128, R2, R3 BEQ R3, msa_large AND $15, R2, R5 XOR R2, R5, R6 ADDVU R1, R6 msa_small: VMOVB W0, (R1) ADDVU $16, R1 SGTU R6, R1, R3 BNE R3, R0, msa_small BEQ R5, R0, done VMOVB W0, -16(R4)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.7K bytes - Viewed (0) -
test/codegen/mathbits.go
// amd64:"NEGL","ADCQ","SBBQ","NEGQ" // loong64: "ADDV", "SGTU" // ppc64x: "ADDC", "ADDE", "ADDZE" // s390x:"ADDE","ADDC\t[$]-1," // mips64:"ADDV","SGTU" // riscv64: "ADD","SLTU" return bits.Add(x, 7, ci) } func AddZ(x, y uint) (r, co uint) { // arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP" // amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ" // loong64: "ADDV", "SGTU" // ppc64x: "ADDC", -"ADDE", "ADDZE"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
src/runtime/memmove_loong64.s
TEXT runtime·memmove<ABIInternal>(SB), NOSPLIT|NOFRAME, $0-24 BNE R6, check RET check: SGTU R4, R5, R7 BNE R7, backward ADDV R4, R6, R9 // end pointer // if the two pointers are not of same alignments, do byte copying SUBVU R5, R4, R7 AND $7, R7 BNE R7, out // if less than 8 bytes, do byte copying SGTU $8, R6, R7 BNE R7, out // do one byte at a time until 8-aligned AND $7, R4, R8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 13 15:04:25 UTC 2024 - 1.8K bytes - Viewed (0) -
src/runtime/memmove_mips64x.s
MOVV from+8(FP), R2 MOVV n+16(FP), R3 BNE R3, check RET check: SGTU R1, R2, R4 BNE R4, backward ADDV R1, R3, R6 // end pointer // if the two pointers are not of same alignments, do byte copying SUBVU R2, R1, R4 AND $7, R4 BNE R4, out // if less than 8 bytes, do byte copying SGTU $8, R3, R4 BNE R4, out // do one byte at a time until 8-aligned AND $7, R1, R5
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.8K bytes - Viewed (0) -
src/internal/bytealg/compare_mips64x.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat Nov 06 10:24:44 UTC 2021 - 1.7K bytes - Viewed (0) -
src/internal/bytealg/compare_loong64.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 13 15:04:25 UTC 2024 - 1.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc2.s
SGT $65536, R4, R5 // 1e02001485781200 SGT $4096, R4, R5 // 3e00001485781200 SGT $65536, R4 // 1e02001484781200 SGT $4096, R4 // 3e00001484781200 SGTU $65536, R4, R5 // 1e02001485f81200 SGTU $4096, R4, R5 // 3e00001485f81200 SGTU $65536, R4 // 1e02001484f81200 SGTU $4096, R4 // 3e00001484f81200 ADDU $65536, R4, R5 // 1e02001485781000 ADDU $4096, R4, R5 // 3e00001485781000 ADDU $65536, R4 // 1e02001484781000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 10 15:50:11 UTC 2023 - 3K bytes - Viewed (0)