"LBU",
	"SW",
	"SH",
	"SB",
	"FENCE",
	"FENCETSO",
	"PAUSE",
	"ADDIW",
	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",

	"MOVBU",
	"MOVD",
	"MOVDF",
	"MOVDW",
	"MOVF",
	"MOVFD",
	"MOVFW",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWD",
	"MOVWF",
	"MOVWL",
	"MOVWR",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULH",
	"MULHU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"SC",
	"SCV",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",

	MOVHU	R4, result+16(FP)	// 64604029
	MOVHU	R4, 1(R5)		// a4044029
	MOVHU	y+8(FP), R4		// 6440402a
	MOVHU	1(R5), R4		// a404402a
	MULU	R4, R5	   		// a5101c00
	MULU	R4, R5, R6		// a6101c00
	MULH	R4, R5	   		// a5901c00
	MULH	R4, R5, R6	   	// a6901c00
	MULHU	R4, R5			// a5101d00
	MULHU	R4, R5, R6		// a6101d00
	REM	R4, R5	  		// a5902000
	REM	R4, R5, R6	  	// a6902000
	REMU	R4, R5	   		// a5902100

		{name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, typ: "Int64"}, // arg0 * arg1
		{name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, typ: "Int32"},
		{name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64"},
		{name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64"},

	LD	(X5), X6				// 03b30200
	LD	4(X5), X6				// 03b34200
	SD	X5, (X6)				// 23305300
	SD	X5, 4(X6)				// 23325300

	// 7.1: Multiplication Operations
	MUL	X5, X6, X7				// b3035302
	MULH	X5, X6, X7				// b3135302
	MULHU	X5, X6, X7				// b3335302
	MULHSU	X5, X6, X7				// b3235302
	MULW	X5, X6, X7				// bb035302
	DIV	X5, X6, X7				// b3435302
	DIVU	X5, X6, X7				// b3535302

		return 0x38 << 15 // mul.w
	case AMULU:
		return 0x38 << 15 // mul.w
	case AMULH:
		return 0x39 << 15 // mulh.w
	case AMULHU:
		return 0x3a << 15 // mulhu.w
	case AMULV:
		return 0x3b << 15 // mul.d
	case AMULVU:
		return 0x3b << 15 // mul.d
	case AMULHV:
		return 0x3c << 15 // mulh.d
	case AMULHVU:
		return 0x3d << 15 // mulhu.d
	case ADIV:
		return 0x40 << 15 // div.w
	case ADIVU:

(Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
(Div8u x y)  => (DIVUW (ZeroExt8to32 x)  (ZeroExt8to32 y))

(Hmul64 ...)  => (MULH  ...)
(Hmul64u ...) => (MULHU ...)
(Hmul32 x y)  => (SRAI [32] (MUL  (SignExt32to64 x) (SignExt32to64 y)))
(Hmul32u x y) => (SRLI [32] (MUL  (ZeroExt32to64 x) (ZeroExt32to64 y)))

		{name: "MNEGW", argLength: 2, reg: gp21, asm: "MNEGW", commutative: true},                                     // -arg0 * arg1, 32-bit
		{name: "MULH", argLength: 2, reg: gp21, asm: "SMULH", commutative: true},                                      // (arg0 * arg1) >> 64, signed

(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))

(Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)

(Mul(32|64)F ...) => ((FMULS|FMUL) ...)

(Div(32|64)F ...) => ((FDIVS|FDIV) ...)

// Lowering float <=> int
(Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x)))

(Div16  x y) => (DIVW  (MOVHreg x) (MOVHreg y))
(Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
(Div8   x y) => (DIVW  (MOVBreg x) (MOVBreg y))
(Div8u  x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))

(Hmul(64|64u) ...) => (MULH(D|DU) ...)
(Hmul32  x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y)))
(Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y)))

(Mod64 x y) => (MODD x y)
(Mod64u ...) => (MODDU ...)