"LDORW",
	"LDP",
	"LDPSW",
	"LDPW",
	"LDXP",
	"LDXPW",
	"LDXR",
	"LDXRB",
	"LDXRH",
	"LDXRW",
	"LSL",
	"LSLW",
	"LSR",
	"LSRW",
	"MADD",
	"MADDW",
	"MNEG",
	"MNEGW",
	"MOVB",
	"MOVBU",
	"MOVD",
	"MOVH",
	"MOVHU",
	"MOVK",
	"MOVKW",
	"MOVN",
	"MOVNW",
	"MOVP",
	"MOVPD",
	"MOVPQ",
	"MOVPS",
	"MOVPSW",
	"MOVPW",
	"MOVW",

(MNEGW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg x)
(MNEGW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
(MNEGW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (NEG <x.Type> x))
(MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c) => (NEG (SLLconst <x.Type> [log64(c)] x))

func noUnsignEXT(t1, t2, t3, t4 uint32, k int64) uint64 {
	var ret uint64

	// arm64:"RORW",-"MOVWU"
	ret += uint64(bits.RotateLeft32(t1, 7))

	// arm64:"MULW",-"MOVWU"
	ret *= uint64(t1 * t2)

	// arm64:"MNEGW",-"MOVWU"
	ret += uint64(-t1 * t3)

	// arm64:"UDIVW",-"MOVWU"
	ret += uint64(t1 / t4)

	// arm64:-"MOVWU"
	ret += uint64(t2 % t3)

	// arm64:"MSUBW",-"MOVWU"
	ret += uint64(t1 - t2*t3)

		{name: "MNEG", argLength: 2, reg: gp21, asm: "MNEG", commutative: true},                                       // -arg0 * arg1
		{name: "MNEGW", argLength: 2, reg: gp21, asm: "MNEGW", commutative: true},                                     // -arg0 * arg1, 32-bit

	LSRW $1, R3, R16                           // 707c0153
	LSR $12, R1, R20                           // 34fc4cd3
	MADDW R13, R23, R3, R10                    // 6a5c0d1b
	MADD R5, R23, R10, R4                      // 445d059b
	MNEGW R0, R9, R21                          // 35fd001b
	MNEG R14, R27, R23                         // 77ff0e9b
	MOVD  R2, R7                               // e70302aa
	MOVW $-24, R20                             // f4028012

			if !(v.Type.Size() <= 4 && l.Uses == 1 && clobber(l)) {
				continue
			}
			v.reset(OpARM64MADDW)
			v.AddArg3(a, x, y)
			return true
		}
		break
	}
	// match: (ADD a l:(MNEGW x y))
	// cond: v.Type.Size() <= 4 && l.Uses==1 && clobber(l)
	// result: (MSUBW a x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			a := v_0
			l := v_1

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MNEGW",
		argLen:      2,
		commutative: true,
		asm:         arm64.AMNEGW,
		reg: regInfo{
			inputs: []inputInfo{