a.Reg = arm64.REG_SXTW + Rnum
			}
		case "SXTX":
			if a.Type == obj.TYPE_MEM {
				a.Index = arm64.REG_SXTX + Rnum
			} else {
				a.Reg = arm64.REG_SXTX + Rnum
			}
		case "LSL":
			a.Index = arm64.REG_LSL + Rnum
		default:
			return errors.New("unsupported general register extension type: " + ext)

		}
	} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
		switch ext {
		case "B8":

	LDXRB (R0), R4                             // 047c5f08
	LDXRH (R12), R26                           // 9a7d5f48
	LSLW R11, R10, R15                         // 4f21cb1a
	LSL R27, R24, R21                          // 1523db9a
	LSLW $5, R7, R22                           // f6681b53
	LSL $57, R17, R2                           // 221a47d3
	LSRW R9, R3, R12                           // 6c24c91a
	LSR R10, R5, R2                            // a224ca9a

		return
	}

	isIndex := false
	num := int16(0)
	isAmount := true // Amount is zero by default
	ext := ""
	if p.peek() == lex.LSH {
		// (Rn)(Rm<<2), the shifted offset register.
		ext = "LSL"
	} else {
		// (Rn)(Rm.UXTW<1), the extended offset register.
		// Rm.UXTW<<3, the extended register.
		p.get('.')
		tok := p.next()
		ext = tok.String()
	}
	if p.peek() == lex.LSH {