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Results 1 - 6 of 6 for UXTW (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	//TODO MOVHW (R22)(R24.SXTX), R4           // c4eaf878
    	MOVH (R26)(R30.UXTW<<1), ZR                // 5f5bbe78
    	MOVW.P -58(R16), R2                        // 02669cb8
    	MOVW.W -216(R19), R8                       // 688e92b8
    	MOVW 4764(R23), R10                        // ea9e92b9
    	MOVW (R8)(R3.UXTW), R17                    // 1149a3b8
    	//TODO LDTR -0x1e(R3), R4                  // 64285eb8
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	MOVD	(R3)(R7.SXTX<<3), R8            // 68f867f8
    	MOVWU	(R5)(R4.UXTW), R10              // aa4864b8
    	MOVBU	(R3)(R9.UXTW), R8               // 68486938
    	MOVBU	(R5)(R8), R10                   // aa686838
    	MOVHU	(R2)(R7.SXTW<<1), R11           // 4bd86778
    	MOVHU	(R1)(R2<<1), R5                 // 25786278
    	MOVB	(R9)(R3.UXTW), R6               // 2649a338
    	MOVB	(R10)(R6), R15                  // 4f69a638
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Jul 24 18:45:14 UTC 2024
    - 95.2K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/arm64.go

    			}
    			a.Reg = arm64.REG_UXTB + Rnum
    		case "UXTH":
    			if a.Type == obj.TYPE_MEM {
    				return errors.New("invalid shift for the register offset addressing mode")
    			}
    			a.Reg = arm64.REG_UXTH + Rnum
    		case "UXTW":
    			// effective address of memory is a base register value and an offset register value.
    			if a.Type == obj.TYPE_MEM {
    				a.Index = arm64.REG_UXTW + Rnum
    			} else {
    				a.Reg = arm64.REG_UXTW + Rnum
    			}
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Sep 29 09:04:58 UTC 2022
    - 10.4K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64error.s

    	MOVD.P	R3, 344(R2)                                      // ERROR "offset out of range [-256,255]"
    	MOVD	(R3)(R7.SXTX<<2), R8                             // ERROR "invalid index shift amount"
    	MOVWU	(R5)(R4.UXTW<<3), R10                            // ERROR "invalid index shift amount"
    	MOVWU	(R5)(R4<<1), R10                                 // ERROR "invalid index shift amount"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/parse.go

    	num := int16(0)
    	isAmount := true // Amount is zero by default
    	ext := ""
    	if p.peek() == lex.LSH {
    		// (Rn)(Rm<<2), the shifted offset register.
    		ext = "LSL"
    	} else {
    		// (Rn)(Rm.UXTW<1), the extended offset register.
    		// Rm.UXTW<<3, the extended register.
    		p.get('.')
    		tok := p.next()
    		ext = tok.String()
    	}
    	if p.peek() == lex.LSH {
    		// parses left shift amount applied after extension: <<Amount
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  6. doc/asm.html

    <code>R0.UXTB&lt;&lt;imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits.
    The <code>imm</code> value can be 0, 1, 2, 3, or 4.
    The other extensions include <code>UXTH</code> (16-bit), <code>UXTW</code> (32-bit), and <code>UXTX</code> (64-bit).
    </li>
    
    <li>
    <code>R0.SXTB</code>
    <br>
    <code>R0.SXTB&lt;&lt;imm</code>:
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
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