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Results 1 - 6 of 6 for UXTW (0.03 sec)
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src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jul 24 18:45:14 UTC 2024 - 95.2K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
} a.Reg = arm64.REG_UXTB + Rnum case "UXTH": if a.Type == obj.TYPE_MEM { return errors.New("invalid shift for the register offset addressing mode") } a.Reg = arm64.REG_UXTH + Rnum case "UXTW": // effective address of memory is a base register value and an offset register value. if a.Type == obj.TYPE_MEM { a.Index = arm64.REG_UXTW + Rnum } else { a.Reg = arm64.REG_UXTW + Rnum }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
num := int16(0) isAmount := true // Amount is zero by default ext := "" if p.peek() == lex.LSH { // (Rn)(Rm<<2), the shifted offset register. ext = "LSL" } else { // (Rn)(Rm.UXTW<1), the extended offset register. // Rm.UXTW<<3, the extended register. p.get('.') tok := p.next() ext = tok.String() } if p.peek() == lex.LSH { // parses left shift amount applied after extension: <<Amount
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Sep 04 18:16:59 UTC 2024 - 36.9K bytes - Viewed (0) -
doc/asm.html
<code>R0.UXTB<<imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits. The <code>imm</code> value can be 0, 1, 2, 3, or 4. The other extensions include <code>UXTH</code> (16-bit), <code>UXTW</code> (32-bit), and <code>UXTX</code> (64-bit). </li> <li> <code>R0.SXTB</code> <br> <code>R0.SXTB<<imm</code>:
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0)