- Sort Score
- Result 10 results
- Languages All
Results 1 - 4 of 4 for SXTB (0.14 sec)
-
src/cmd/asm/internal/arch/arm64.go
return errors.New("invalid shift for the register offset addressing mode") } a.Reg = arm64.REG_UXTX + Rnum case "SXTB": if a.Type == obj.TYPE_MEM { return errors.New("invalid shift for the register offset addressing mode") } a.Reg = arm64.REG_SXTB + Rnum case "SXTH": if a.Type == obj.TYPE_MEM { return errors.New("invalid shift for the register offset addressing mode") }
Go - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Thu Sep 29 09:04:58 GMT 2022 - 10.4K bytes - Viewed (0) -
doc/asm.html
</li> <li> <code>R0.SXTB</code> <br> <code>R0.SXTB<<imm</code>: <code>SXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and sign-extend it to the size of <code>R0</code>. <code>R0.SXTB<<imm</code>: left shift the result of <code>R0.SXTB</code> by <code>imm</code> bits. The <code>imm</code> value can be 0, 1, 2, 3, or 4.
HTML - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Tue Nov 28 19:15:27 GMT 2023 - 36.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
ADC R0, R2, R12 // 4c00009a ADCSW R9, R21, R6 // a602093a ADCS R23, R22, R22 // d60217ba ADDW R5.UXTH, R8, R9 // 0921250b ADD R8.SXTB<<3, R23, R14 // ee8e288b ADDW $3076, R17, R3 // 23123011 ADDW $(3076<<12), R17, R3 // ADDW $12599296, R17, R3 // 23127011
Others - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm64.s
Others - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0)