return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_UXTB + Rnum
		case "UXTH":
			if a.Type == obj.TYPE_MEM {
				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_UXTH + Rnum
		case "UXTW":
			// effective address of memory is a base register value and an offset register value.
			if a.Type == obj.TYPE_MEM {

	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
	SUBS	R3.UXTX, R8, R9                 // 096123eb
	SUBSW	R17.UXTH, R15, R21              // f521316b
	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
	CMP	R2.SXTH, R13                    // bfa122eb
	CMN	R1.SXTX<<2, R10                 // 5fe921ab
	CMPW	R2.UXTH<<3, R11                 // 7f2d226b

	ADC R0, R2, R12                            // 4c00009a
	ADCSW R9, R21, R6                          // a602093a
	ADCS R23, R22, R22                         // d60217ba
	ADDW R5.UXTH, R8, R9                       // 0921250b
	ADD R8.SXTB<<3, R23, R14                   // ee8e288b
	ADDW $3076, R17, R3                        // 23123011

<code>R0.UXTB&lt;&lt;imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits.
The <code>imm</code> value can be 0, 1, 2, 3, or 4.
The other extensions include <code>UXTH</code> (16-bit), <code>UXTW</code> (32-bit), and <code>UXTX</code> (64-bit).
</li>

<li>
<code>R0.SXTB</code>
<br>
<code>R0.SXTB&lt;&lt;imm</code>: