"MOVKW",
	"MOVN",
	"MOVNW",
	"MOVP",
	"MOVPD",
	"MOVPQ",
	"MOVPS",
	"MOVPSW",
	"MOVPW",
	"MOVW",
	"MOVWU",
	"MOVZ",
	"MOVZW",
	"MRS",
	"MSR",
	"MSUB",
	"MSUBW",
	"MUL",
	"MULW",
	"MVN",
	"MVNW",
	"NEG",
	"NEGS",
	"NEGSW",
	"NEGW",
	"NGC",
	"NGCS",
	"NGCSW",
	"NGCW",
	"NOOP",
	"ORN",
	"ORNW",
	"ORR",
	"ORRW",

(MSUBW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
(MSUBW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
(MSUBW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
(MSUBW a x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))

func MULS(a, b, c uint32) (uint32, uint32, uint32) {
	// arm/7:`MULS`,-`MUL\s`
	// arm/6:`SUB`,`MUL\s`,-`MULS`
	// arm64:`MSUBW`,-`MULW`
	r0 := c - a*b
	// arm/7:`MULS`,-`MUL\s`
	// arm/6:`SUB`,`MUL\s`,-`MULS`
	// arm64:`MSUBW`,-`MULW`
	r1 := a - c*79
	// arm/7:`SUB`,-`MULS`,-`MUL\s`
	// arm64:`SUB`,-`MSUBW`,-`MULW`
	// ppc64x:`SUB`,-`MULLD`
	r2 := c - b*64
	return r0, r1, r2
}

	ret *= uint64(t1 * t2)

	// arm64:"MNEGW",-"MOVWU"
	ret += uint64(-t1 * t3)

	// arm64:"UDIVW",-"MOVWU"
	ret += uint64(t1 / t4)

	// arm64:-"MOVWU"
	ret += uint64(t2 % t3)

	// arm64:"MSUBW",-"MOVWU"
	ret += uint64(t1 - t2*t3)

	// arm64:"MADDW",-"MOVWU"
	ret += uint64(t3*t4 + t2)

	// arm64:"REVW",-"MOVWU"
	ret += uint64(bits.ReverseBytes32(t1))

	// arm64:"RBITW",-"MOVWU"

	if a-b*c > 0 {
		return 1
	}

	// arm64:`CMP`,-`MSUB`,`MUL`,`(BMI|BPL)`
	if b-c*d >= 0 {
		return 2
	}

	// arm64:`CMPW`,-`MSUBW`,`MULW`,`(BMI|BPL)`
	if e-f*g < 0 {
		return 5
	}

	// arm64:`CMPW`,-`MSUBW`,`MULW`,`(BMI|BPL)`
	if f-g*h >= 0 {
		return 6
	}
	return 0
}

func CmpToZero_ex5(e, f int32, u uint32) int {
	// arm:`CMN`,-`ADD`,`BEQ`,`(BMI|BPL)`

Examples:

	MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
	MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
	STLRH R21, (R19)      <=>    stlrh w21, [x19]

(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>

Examples:

	MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3

		return true
	}
	// match: (MSUBW a _ (MOVDconst [c]))
	// cond: int32(c)==0
	// result: (MOVWUreg a)
	for {
		a := v_0
		if v_2.Op != OpARM64MOVDconst {
			break
		}
		c := auxIntToInt64(v_2.AuxInt)
		if !(int32(c) == 0) {
			break
		}
		v.reset(OpARM64MOVWUreg)
		v.AddArg(a)
		return true
	}
	// match: (MSUBW a x (MOVDconst [c]))
	// cond: int32(c)==1

		{name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"},     // +arg0 + (arg1 * arg2), 32-bit
		{name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"},       // +arg0 - (arg1 * arg2)
		{name: "MSUBW", argLength: 3, reg: gp31, asm: "MSUBW"},     // +arg0 - (arg1 * arg2), 32-bit

		// shifts
		{name: "SLL", argLength: 2, reg: gp21, asm: "LSL"},                        // arg0 << arg1, shift amount is mod 64

	MSR $6, DAIFClr                            // ff4603d5
	MRS ELR_EL1, R8                            // 284038d5
	MSR R16, ELR_EL1                           // 304018d5
	MRS DCZID_EL0, R3                          // e3003bd5
	MSUBW R1, R1, R12, R5                      // 8585011b
	MSUB R19, R16, R26, R2                     // 42c3139b
	MULW R26, R5, R22                          // b67c1a1b
	MUL R4, R3, R0                             // 607c049b

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "MSUBW",
		argLen: 3,
		asm:    arm64.AMSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30