"TST",
	"TSTW",
	"UBFIZ",
	"UBFIZW",
	"UBFM",
	"UBFMW",
	"UBFX",
	"UBFXW",
	"UCVTFD",
	"UCVTFS",
	"UCVTFWD",
	"UCVTFWS",
	"UDIV",
	"UDIVW",
	"UMADDL",
	"UMNEGL",
	"UMSUBL",
	"UMULH",
	"UMULL",
	"UREM",
	"UREMW",
	"UXTB",
	"UXTBW",
	"UXTH",
	"UXTHW",
	"UXTW",
	"VADD",
	"VADDP",
	"VADDV",
	"VAND",
	"VBCAX",
	"VBIF",
	"VBIT",

Examples:

	MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
	MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
	STLRH R21, (R19)      <=>    stlrh w21, [x19]

(2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>

Examples:

	MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3

	case STRH, STURH:
		op = "MOVH" + suffix
		args[0], args[1] = args[1], args[0]

	case TBNZ, TBZ:
		args[0], args[1], args[2] = args[2], args[0], args[1]

	case MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[2], args[3] = args[3], args[2]
	case STLR:
		if r, ok := inst.Args[0].(Reg); ok {

	UMIN:      "UMIN",
	UMINP:     "UMINP",
	UMINV:     "UMINV",
	UMLAL:     "UMLAL",
	UMLAL2:    "UMLAL2",
	UMLSL:     "UMLSL",
	UMLSL2:    "UMLSL2",
	UMNEGL:    "UMNEGL",
	UMOV:      "UMOV",
	UMSUBL:    "UMSUBL",
	UMULH:     "UMULH",
	UMULL:     "UMULL",
	UMULL2:    "UMULL2",
	UQADD:     "UQADD",
	UQRSHL:    "UQRSHL",
	UQRSHRN:   "UQRSHRN",
	UQRSHRN2:  "UQRSHRN2",
	UQSHL:     "UQSHL",

	UBFX $33, R17, $25, R5                     // 25e661d3
	UDIVW R8, R21, R15                         // af0ac81a
	UDIV R2, R19, R21                          // 750ac29a
	UMADDL R0, R20, R17, R17                   // 3152a09b
	UMSUBL R22, R4, R3, R7                     // 6790b69b
	UMNEGL R3, R19, R1                         // 61fea39b
	UMULH R24, R20, R24                        // 987ed89b
	UMULL R19, R22, R19                        // d37eb39b

{"Name":"UMNEGL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMSUBL instruction."},
{"Name":"UMSUBL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMNEGL."},