min, max   int64  // min <= value <= max, signed
	umin, umax uint64 // umin <= value <= umax, unsigned
}

func (l limit) String() string {
	return fmt.Sprintf("sm,SM,um,UM=%d,%d,%d,%d", l.min, l.max, l.umin, l.umax)
}

func (l limit) intersect(l2 limit) limit {
	if l.min < l2.min {
		l.min = l2.min
	}
	if l.umin < l2.umin {
		l.umin = l2.umin
	}
	if l.max > l2.max {
		l.max = l2.max
	}

	UBFX:      "UBFX",
	UCVTF:     "UCVTF",
	UDIV:      "UDIV",
	UHADD:     "UHADD",
	UHSUB:     "UHSUB",
	UMADDL:    "UMADDL",
	UMAX:      "UMAX",
	UMAXP:     "UMAXP",
	UMAXV:     "UMAXV",
	UMIN:      "UMIN",
	UMINP:     "UMINP",
	UMINV:     "UMINV",
	UMLAL:     "UMLAL",
	UMLAL2:    "UMLAL2",
	UMLSL:     "UMLSL",
	UMLSL2:    "UMLSL2",
	UMNEGL:    "UMNEGL",
	UMOV:      "UMOV",
	UMSUBL:    "UMSUBL",

{"Name":"UMAXV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"UMIN","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},