"UBFIZW",
	"UBFM",
	"UBFMW",
	"UBFX",
	"UBFXW",
	"UCVTFD",
	"UCVTFS",
	"UCVTFWD",
	"UCVTFWS",
	"UDIV",
	"UDIVW",
	"UMADDL",
	"UMNEGL",
	"UMSUBL",
	"UMULH",
	"UMULL",
	"UREM",
	"UREMW",
	"UXTB",
	"UXTBW",
	"UXTH",
	"UXTHW",
	"UXTW",
	"VADD",
	"VADDP",
	"VADDV",
	"VAND",
	"VBCAX",
	"VBIF",
	"VBIT",
	"VBSL",
	"VCMEQ",

	UMULL_LE:          "UMULL.LE",
	UMULL:             "UMULL",
	UMULL_ZZ:          "UMULL.ZZ",
	UMULL_S_EQ:        "UMULL.S.EQ",
	UMULL_S_NE:        "UMULL.S.NE",
	UMULL_S_CS:        "UMULL.S.CS",
	UMULL_S_CC:        "UMULL.S.CC",
	UMULL_S_MI:        "UMULL.S.MI",
	UMULL_S_PL:        "UMULL.S.PL",
	UMULL_S_VS:        "UMULL.S.VS",
	UMULL_S_VC:        "UMULL.S.VC",
	UMULL_S_HI:        "UMULL.S.HI",

	UMINV:     "UMINV",
	UMLAL:     "UMLAL",
	UMLAL2:    "UMLAL2",
	UMLSL:     "UMLSL",
	UMLSL2:    "UMLSL2",
	UMNEGL:    "UMNEGL",
	UMOV:      "UMOV",
	UMSUBL:    "UMSUBL",
	UMULH:     "UMULH",
	UMULL:     "UMULL",
	UMULL2:    "UMULL2",
	UQADD:     "UQADD",
	UQRSHL:    "UQRSHL",
	UQRSHRN:   "UQRSHRN",
	UQRSHRN2:  "UQRSHRN2",
	UQSHL:     "UQSHL",
	UQSHRN:    "UQSHRN",
	UQSHRN2:   "UQSHRN2",

{"Name":"UMULL, UMULL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},

		{name: "MULL", argLength: 2, reg: gp21, asm: "SMULL", commutative: true},                                      // arg0 * arg1, signed, 32-bit mult results in 64-bit
		{name: "UMULL", argLength: 2, reg: gp21, asm: "UMULL", commutative: true},                                     // arg0 * arg1, unsigned, 32-bit mult results in 64-bit

	UMADDL R0, R20, R17, R17                   // 3152a09b
	UMSUBL R22, R4, R3, R7                     // 6790b69b
	UMNEGL R3, R19, R1                         // 61fea39b
	UMULH R24, R20, R24                        // 987ed89b
	UMULL R19, R22, R19                        // d37eb39b
	UXTBW R2, R6                               // 461c0053
	UXTHW R7, R20                              // f43c0053
	VCNT V0.B8, V0.B8                          // 0058200e

(Mul(32|16|8) ...) => (MULW ...)
(Mul(32|64)F  ...) => (FMUL(S|D) ...)

(Hmul64  ...) => (MULH ...)
(Hmul64u ...) => (UMULH ...)
(Hmul32  x y) => (SRAconst (MULL <typ.Int64> x y) [32])
(Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
(Select0 (Mul64uhilo x y)) => (UMULH x y)
(Select1 (Mul64uhilo x y)) => (MUL x y)

(Div64 [false] x y) => (DIV  x y)
(Div32 [false] x y) => (DIVW x y)

			rel.Off = int32(c.pc)
			rel.Siz = 4
			rel.Sym = p.To.Sym
			rel.Add = p.To.Offset
			rel.Type = objabi.R_ADDR
			o1 = 0
		}

	case 15: /* mul/mneg/umulh/umull r,[r,]r; madd/msub/fmadd/fmsub/fnmadd/fnmsub Rm,Ra,Rn,Rd */
		o1 = c.oprrr(p, p.As)

		rf := int(p.From.Reg)
		rt := int(p.To.Reg)
		var r int
		var ra int
		if p.From3Type() == obj.TYPE_REG {

	}
}
func rewriteValueARM64_OpHmul32u(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Hmul32u x y)
	// result: (SRAconst (UMULL <typ.UInt64> x y) [32])
	for {
		x := v_0
		y := v_1
		v.reset(OpARM64SRAconst)
		v.AuxInt = int64ToAuxInt(32)
		v0 := b.NewValue0(v.Pos, OpARM64UMULL, typ.UInt64)
		v0.AddArg2(x, y)

			},
			outputs: []outputInfo{
				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "UMULL",
		argLen:      2,
		commutative: true,
		asm:         arm64.AUMULL,
		reg: regInfo{
			inputs: []inputInfo{