VMOV    V1.D[0], R0
	VMOV    V1.D[1], R1
	MOVD    R0, r1+0(FP)
	MOVD    R1, r2+8(FP)
	RET

// testmovk() uint64
TEXT ·testmovk(SB), NOSPLIT, $0-8
	MOVD	$0, R0
	MOVK	$(40000<<48), R0
	MOVD	R0, ret+0(FP)

The current Go assembler does not accept zero shifts, such as "op $0, Rd" and "op $(0<<(16|32|48)), Rd" instructions.

Examples:

	MOVK $(10<<32), R20     <=>      movk x20, #10, lsl #32
	MOVZW $(20<<16), R8     <=>      movz w8, #20, lsl #16
	MOVK $(0<<16), R10 will be reported as an error by the assembler.

Special Cases.

(1) umov is written as VMOV.

(2) br is renamed JMP, blr is renamed CALL.

	"LDXR",
	"LDXRB",
	"LDXRH",
	"LDXRW",
	"LSL",
	"LSLW",
	"LSR",
	"LSRW",
	"MADD",
	"MADDW",
	"MNEG",
	"MNEGW",
	"MOVB",
	"MOVBU",
	"MOVD",
	"MOVH",
	"MOVHU",
	"MOVK",
	"MOVKW",
	"MOVN",
	"MOVNW",
	"MOVP",
	"MOVPD",
	"MOVPQ",
	"MOVPS",
	"MOVPSW",
	"MOVPW",
	"MOVW",
	"MOVWU",
	"MOVZ",
	"MOVZW",
	"MRS",
	"MSR",
	"MSUB",

			t.Errorf("%v: got: a=0x%x, b=0x%x, want: a=0x%x, b=0x%x", test.op, gotA, gotB, test.wantA, test.wantB)
		}
	}
}

func testmovk() uint64

// TestMOVK makes sure MOVK with a very large constant works. See issue 52261.
func TestMOVK(t *testing.T) {
	x := testmovk()
	want := uint64(40000 << 48)
	if x != want {
		t.Errorf("Got %x want %x\n", x, want)
	}

	STP	(R26, R27), 700(R2)                              // ERROR "cannot use REGTMP as source"
	MOVK	$0, R10                                          // ERROR "zero shifts cannot be handled correctly"
	MOVK	$(0<<32), R10                                    // ERROR "zero shifts cannot be handled correctly"
	TLBI	PLDL1KEEP                                        // ERROR "illegal argument"

	MOVKW $(3905<<0), R21                      // MOVKW $3905, R21              // 35e88172
	MOVKW $(3905<<16), R21                     // MOVKW $255918080, R21         // 35e8a172
	MOVK $(3905<<32), R21                      // MOVK $16771847290880, R21     // 35e8c1f2
	MOVD $0, R5                                // e5031faa
	MSR $1, SPSel                              // bf4100d5
	MSR $9, DAIFSet                            // df4903d5

	C_BITCON   // bitfield and logical immediate masks
	C_ADDCON2  // 24-bit constant
	C_LCON     // 32-bit constant
	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
	C_VCON     // 64-bit constant
	C_FCON     // floating-point constant
	C_VCONADDR // 64-bit memory address

	{0xff800000, 0xd2800000, MOVZ, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
	// MOVK <Wd>, #<imm>{, LSL #<shift>}
	{0xff800000, 0x72800000, MOVK, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil},
	// MOVK <Xd>, #<imm>{, LSL #<shift>}
	{0xff800000, 0xf2800000, MOVK, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
	// MRS <Xt>, <systemreg>

		o1 = c.omovconst(p.As, p, &p.From, int(p.To.Reg))

	case 33: /* movk $uimm16 << pos */
		o1 = c.opirr(p, p.As)

		d := p.From.Offset
		if d == 0 {
			c.ctxt.Diag("zero shifts cannot be handled correctly: %v", p)
		}
		s := movcon(d)
		if s < 0 || s >= 4 {
			c.ctxt.Diag("bad constant for MOVK: %#x\n%v", uint64(d), p)
		}
		if (o1&S64) == 0 && s >= 2 {

			}

			// R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
			// turn ADRP to MOVZ
			o0 = 0xd2a00000 | uint32(o0&0x1f) | (uint32((v>>16)&0xffff) << 5)
			// R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
			// turn LD64 to MOVK
			if v&3 != 0 {
				ldr.Errorf(s, "invalid address: %x for relocation type: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC", v)
			}
			o1 = 0xf2800000 | uint32(o1&0x1f) | (uint32(v&0xffff) << 5)