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Results 1 - 10 of 27 for SRAW (0.03 sec)
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src/math/acosh_s390x.s
SRAD $32, R5 MOVH $0x0, R1 SUBW R5, R3 FMOVD $0, F10 RISBGZ $32, $47, $0, R3, R4 RISBGZ $57, $60, $51, R3, R3 BYTE $0x18 //lr %r2,%r4 BYTE $0x24 RISBGN $0, $31, $32, R4, R1 SUBW $0x100000, R2 SRAW $8, R2, R2 ORW $0x45000000, R2 L5: LDGR R1, F0 FMOVD 104(R9), F2 FMADD F8, F0, F2 FMOVD 96(R9), F4 WFMADB V10, V0, V2, V0 FMOVD 88(R9), F6 FMOVD 80(R9), F2 WFMADB V0, V6, V4, V6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 4.3K bytes - Viewed (0) -
src/net/http/responsewrite_test.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 07 01:07:32 UTC 2022 - 6.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"LWU", "LH", "LHU", "LB", "LBU", "SW", "SH", "SB", "FENCE", "FENCETSO", "PAUSE", "ADDIW", "SLLIW", "SRLIW", "SRAIW", "ADDW", "SLLW", "SRLW", "SUBW", "SRAW", "LD", "SD", "MUL", "MULH", "MULHU", "MULHSU", "MULW", "DIV", "DIVU", "REM", "REMU", "DIVW", "DIVUW", "REMW", "REMUW", "LRD", "SCD", "LRW", "SCW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/net/http/requestwrite_test.go
t.Errorf("writing #%d, err = %q, want %q", i, g, e) continue } if err != nil { continue } if tt.WantWrite != "" { sraw := braw.String() if sraw != tt.WantWrite { t.Errorf("Test %d, expecting:\n%s\nGot:\n%s\n", i, tt.WantWrite, sraw) continue } } if tt.WantProxy != "" { setBody() var praw strings.Builder err = tt.Req.WriteProxy(&praw)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 07 01:07:32 UTC 2022 - 23.3K bytes - Viewed (0) -
src/math/asinh_s390x.s
BYTE $0xFF LGDR F0, R5 SRAD $32, R5 MOVH $0x0, R2 SUBW R5, R3 FMOVD $0, F8 RISBGZ $32, $47, $0, R3, R4 BYTE $0x18 //lr %r1,%r4 BYTE $0x14 RISBGN $0, $31, $32, R4, R2 SUBW $0x100000, R1 SRAW $8, R1, R1 ORW $0x45000000, R1 BR L6 L2: MOVD $0x30000000, R2 CMPW R1, R2 BGT L16 FMOVD 200(R9), F2 FMADD F2, F0, F0 L1: FMOVD F0, ret+8(FP) RET L14: LTDBR F0, F0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 5.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
test/codegen/shift.go
return v >> (s & 31) } func rshMask32x64(v int32, s uint64) int32 { // arm64:"ASR",-"AND" // ppc64x:"ISEL",-"ORN" // riscv64:"SRAW","OR","SLTIU" // s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func rsh5Mask32x64(v int32, s uint64) int32 { // riscv64:"SRAW",-"OR",-"SLTIU" return v >> (s & 31) } func lshMask64x32(v int64, s uint32) int64 { // arm64:"LSL",-"AND"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
SRLW X5, X6, X7 // bb535300 SUBW X5, X6, X7 // bb035340 SRAW X5, X6, X7 // bb535340 ADDIW $1, X6 // 1b031300 SLLIW $1, X6 // 1b131300 SRLIW $1, X6 // 1b531300 SRAIW $1, X6 // 1b531340 ADDW X5, X7 // bb835300 SLLW X5, X7 // bb935300 SRLW X5, X7 // bbd35300 SUBW X5, X7 // bb835340 SRAW X5, X7 // bbd35340 ADDW $1, X6 // 1b031300 SLLW $1, X6 // 1b131300
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
"MOVDGE", "MOVDGT", "MOVDLE", "MOVDLT", "MOVDNE", "LOCR", "LOCGR", "FLOGR", "POPCNT", "AND", "ANDW", "OR", "ORW", "XOR", "XORW", "SLW", "SLD", "SRW", "SRAW", "SRD", "SRAD", "RLL", "RLLG", "RNSBG", "RXSBG", "ROSBG", "RNSBGT", "RXSBGT", "ROSBGT", "RISBG", "RISBGN", "RISBGZ", "RISBGNZ", "RISBHG", "RISBLG", "RISBHGZ",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0)