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Results 1 - 10 of 22 for SRW (0.02 sec)

  1. src/cmd/compile/internal/ssa/rewrite_test.go

    		}
    	}
    }
    
    func TestMergePPC64ClrlsldiSrw(t *testing.T) {
    	tests := []struct {
    		clrlsldi int32
    		srw      int64
    		valid    bool
    		rotate   int64
    		mask     uint64
    	}{
    		// ((x>>4)&0xFF)<<4
    		{newPPC64ShiftAuxInt(4, 56, 63, 64), 4, true, 0, 0xFF0},
    		// ((x>>4)&0xFFFF)<<4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 15 21:57:02 UTC 2021
    - 6.9K bytes
    - Viewed (0)
  2. test/codegen/memcombine.go

    	// ppc64le:"MOVW",-"MOVH",-"SRW"
    	p.a = uint16(x)
    	// amd64:-"MOVW",-"SHRL"
    	// arm64:-"MOVH",-"UBFX"
    	// ppc64le:-"MOVH",-"SRW"
    	p.b = uint16(x >> 16)
    }
    func store16be(p *struct{ a, b uint16 }, x uint32) {
    	// ppc64:"MOVW",-"MOVH",-"SRW"
    	// s390x:"MOVW",-"MOVH",-"SRW"
    	p.a = uint16(x >> 16)
    	// ppc64:-"MOVH",-"SRW"
    	// s390x:-"MOVH",-"SRW"
    	p.b = uint16(x)
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 21 19:45:41 UTC 2024
    - 29.7K bytes
    - Viewed (0)
  3. test/codegen/shift.go

    	c[1] = c[((v>>7)&0x3F)<<7]
    }
    
    func checkShiftMask(a uint32, b uint64, z []uint32, y []uint64) {
    	_ = y[128]
    	_ = z[128]
    	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"
    	z[0] = uint32(uint8(a >> 5))
    	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"
    	z[1] = uint32(uint8((a >> 4) & 0x7e))
    	// ppc64x: "RLWNM\t[$]25, R[0-9]+, [$]27, [$]29, R[0-9]+"
    	z[2] = uint32(uint8(a>>7)) & 0x1c
    	// ppc64x: -"MOVWZ"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (Lsh8x(64|32|16|8)   x y) && shiftIsBounded(v) => (SLW x y)
    (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
    (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
    (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW (MOVHZreg x) y)
    (Rsh8Ux(64|32|16|8)  x y) && shiftIsBounded(v) => (SRW (MOVBZreg x) y)
    (Rsh64x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAD x y)
    (Rsh32x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAW x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/ppc64/anames.go

    	"NOR",
    	"NORCC",
    	"OR",
    	"ORCC",
    	"ORN",
    	"ORNCC",
    	"ORIS",
    	"REM",
    	"REMU",
    	"RFI",
    	"RLWMI",
    	"RLWMICC",
    	"RLWNM",
    	"RLWNMCC",
    	"CLRLSLWI",
    	"SLW",
    	"SLWCC",
    	"SRW",
    	"SRAW",
    	"SRAWCC",
    	"SRWCC",
    	"STBCCC",
    	"STHCCC",
    	"STSW",
    	"STWCCC",
    	"SUB",
    	"SUBCC",
    	"SUBVCC",
    	"SUBC",
    	"SUBCCC",
    	"SUBCV",
    	"SUBCVCC",
    	"SUBME",
    	"SUBMECC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  6. src/math/log10_s390x.s

    	BYTE    $0x1C
    	FMOVD   F0, x-8(SP)
    	WORD    $0x5B20F008     //s %r2, 8(%r15)
    	RISBGZ	$57, $60, $51, R2, R3
    	ANDW    $0xFFFF0000, R2
    	RISBGN	$0, $31, $32, R2, R1
    	ADDW    $0x4000000, R2
    	BLEU    L17
    L8:
    	SRW     $8, R2, R2
    	ORW     $0x45000000, R2
    L4:
    	FMOVD   log10rodataL19<>+120(SB), F2
    	LDGR    R1, F4
    	WFMADB  V4, V0, V2, V0
    	FMOVD   log10rodataL19<>+112(SB), F4
    	FMOVD   log10rodataL19<>+104(SB), F6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 4.7K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/s390x/anames.go

    	"MOVDEQ",
    	"MOVDGE",
    	"MOVDGT",
    	"MOVDLE",
    	"MOVDLT",
    	"MOVDNE",
    	"LOCR",
    	"LOCGR",
    	"FLOGR",
    	"POPCNT",
    	"AND",
    	"ANDW",
    	"OR",
    	"ORW",
    	"XOR",
    	"XORW",
    	"SLW",
    	"SLD",
    	"SRW",
    	"SRAW",
    	"SRD",
    	"SRAD",
    	"RLL",
    	"RLLG",
    	"RNSBG",
    	"RXSBG",
    	"ROSBG",
    	"RNSBGT",
    	"RXSBGT",
    	"ROSBGT",
    	"RISBG",
    	"RISBGN",
    	"RISBGZ",
    	"RISBGNZ",
    	"RISBHG",
    	"RISBLG",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Sep 05 16:41:03 UTC 2023
    - 7.1K bytes
    - Viewed (0)
  8. src/math/atanh_s390x.s

    	BR  L1
    L5:
    	WORD    $0xED005070 //ddb   %f0,.L15-.L10(%r5)
    	BYTE    $0x00
    	BYTE    $0x1D
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L9:
    	FMOVD   F0, F2
    	MOVD    $·atanhtabh2075<>+0(SB), R2
    	SRW $31, R1, R1
    	FMOVD   104(R5), F4
    	MOVW    R1, R1
    	SLD $3, R1, R1
    	WORD    $0x68012000 //ld    %f0,0(%r1,%r2)
    	WFMADB  V2, V4, V0, V4
    	VLEG    $0, 96(R5), V16
    	FDIV    F4, F2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 23 20:52:57 UTC 2023
    - 5.1K bytes
    - Viewed (0)
  9. src/math/log1p_s390x.s

    	VLEG	$0, 0(R1), V18
    	MOVD	$·log1pc5<>+0(SB), R1
    	VLEG	$0, 0(R1), V16
    	MOVD	R2, R5
    	LGDR	F4, R3
    	WORD	$0xC0190006	//iilf	%r1,425983
    	BYTE	$0x7F
    	BYTE	$0xFF
    	SRAD	$32, R3, R3
    	SUBW	R3, R1
    	SRW	$16, R1, R1
    	BYTE	$0x18	//lr	%r4,%r1
    	BYTE	$0x41
    	RISBGN	$0, $15, $48, R4, R2
    	RISBGN	$16, $31, $32, R4, R5
    	MOVW	R0, R6
    	MOVW	R3, R7
    	CMPBGT	R6, R7, L8
    	WFCEDBS	V4, V4, V6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 5.1K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/s390x.s

    	XORW	-1(R1), R2            // e3201fffff57
    
    	// shift and rotate instructions
    	SRD	$4, R4, R7              // eb740004000c
    	SRD	R1, R4, R7              // eb741000000c
    	SRW	$4, R4, R7              // eb74000400de
    	SRW	R1, R4, R7              // eb74100000de
    	SLW	$4, R3, R6              // eb63000400df
    	SLW	R2, R3, R6              // eb63200000df
    	SLD	$4, R3, R6              // eb630004000d
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 22 03:55:32 UTC 2023
    - 21.6K bytes
    - Viewed (0)
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