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Results 1 - 10 of 17 for shiftIsBounded (0.32 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Lsh16x8  <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt8to64  y))))
    (Lsh16x16 <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
    (Lsh16x32 <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
    (Lsh16x64 <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (Lsh16x16 <t> x y)
    	// cond: !shiftIsBounded(v)
    	// result: (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
    	for {
    		t := v.Type
    		x := v_0
    		y := v_1
    		if !(!shiftIsBounded(v)) {
    			break
    		}
    		v.reset(OpRISCV64AND)
    		v0 := b.NewValue0(v.Pos, OpRISCV64SLL, t)
    		v0.AddArg2(x, y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/generic.rules

    ((Add64|Or64|Xor64) left:(Lsh64x16 x y) right:(Rsh64Ux16 x (Sub16 (Const16 [64]) y))) && (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 64) => (RotateLeft64 x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 16 22:21:05 UTC 2024
    - 135.3K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (Rsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> x y)
    (Rsh32x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt32to64 x) y)
    (Rsh16x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt16to64 x) y)
    (Rsh8x(64|32|16|8)  <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt8to64 x) y)
    
    // unsigned right shift
    (Rsh64Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewritegeneric.go

    				continue
    			}
    			v.reset(OpRotateLeft16)
    			v.AddArg2(x, y)
    			return true
    		}
    		break
    	}
    	// match: (Add16 left:(Lsh16x32 x y) right:(Rsh16Ux32 x (Sub32 (Const32 [16]) y)))
    	// cond: (shiftIsBounded(left) || shiftIsBounded(right)) && canRotate(config, 16)
    	// result: (RotateLeft16 x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 22 18:24:47 UTC 2024
    - 812.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewrite386.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Lsh16x16 <t> x y)
    	// cond: !shiftIsBounded(v)
    	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
    	for {
    		t := v.Type
    		x := v_0
    		y := v_1
    		if !(!shiftIsBounded(v)) {
    			break
    		}
    		v.reset(Op386ANDL)
    		v0 := b.NewValue0(v.Pos, Op386SHLL, t)
    		v0.AddArg2(x, y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 21:05:46 UTC 2023
    - 262.4K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/rewriteARM64.go

    	// match: (Lsh16x16 <t> x y)
    	// cond: shiftIsBounded(v)
    	// result: (SLL <t> x y)
    	for {
    		t := v.Type
    		x := v_0
    		y := v_1
    		if !(shiftIsBounded(v)) {
    			break
    		}
    		v.reset(OpARM64SLL)
    		v.Type = t
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (Lsh16x16 <t> x y)
    	// cond: !shiftIsBounded(v)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewritePPC64.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (Lsh16x16 x y)
    	// cond: shiftIsBounded(v)
    	// result: (SLD x y)
    	for {
    		x := v_0
    		y := v_1
    		if !(shiftIsBounded(v)) {
    			break
    		}
    		v.reset(OpPPC64SLD)
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (Lsh16x16 <t> x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteS390X.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (Lsh16x16 x y)
    	// cond: shiftIsBounded(v)
    	// result: (SLW x y)
    	for {
    		x := v_0
    		y := v_1
    		if !(shiftIsBounded(v)) {
    			break
    		}
    		v.reset(OpS390XSLW)
    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (Lsh16x16 <t> x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 395.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteAMD64.go

    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Lsh16x16 <t> x y)
    	// cond: !shiftIsBounded(v)
    	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
    	for {
    		t := v.Type
    		x := v_0
    		y := v_1
    		if !(!shiftIsBounded(v)) {
    			break
    		}
    		v.reset(OpAMD64ANDL)
    		v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t)
    		v0.AddArg2(x, y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
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