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Results 1 - 10 of 18 for ORW (0.03 sec)
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src/math/floor_386.s
#include "textflag.h" // func archCeil(x float64) float64 TEXT ·archCeil(SB),NOSPLIT,$0 FMOVD x+0(FP), F0 // F0=x FSTCW -2(SP) // save old Control Word MOVW -2(SP), AX ANDW $0xf3ff, AX ORW $0x0800, AX // Rounding Control set to +Inf MOVW AX, -4(SP) // store new Control Word FLDCW -4(SP) // load new Control Word FRNDINT // F0=Ceil(x) FLDCW -2(SP) // load old Control Word
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 1.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
OR $65536, R1 // c01d00010000 OR $-2, R1 // c0a1fffffffeb981001a ORW R1, R2 // 1621 ORW R1, R2, R3 // b9f62031 ORW $1, R1 // a51b0001 ORW $131071, R1 // c01d0001ffff ORW $65536, R1 // a51a0001 ORW $-2, R1 // c01dfffffffe XOR R1, R2 // b9820021 XOR R1, R2, R3 // b9e72031
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/math/log10_s390x.s
FMOVD F0, x-8(SP) WORD $0x5B20F008 //s %r2, 8(%r15) RISBGZ $57, $60, $51, R2, R3 ANDW $0xFFFF0000, R2 RISBGN $0, $31, $32, R2, R1 ADDW $0x4000000, R2 BLEU L17 L8: SRW $8, R2, R2 ORW $0x45000000, R2 L4: FMOVD log10rodataL19<>+120(SB), F2 LDGR R1, F4 WFMADB V4, V0, V2, V0 FMOVD log10rodataL19<>+112(SB), F4 FMOVD log10rodataL19<>+104(SB), F6 WFMADB V0, V6, V4, V6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 4.7K bytes - Viewed (0) -
src/math/acosh_s390x.s
MOVH $0x0, R1 SUBW R5, R3 FMOVD $0, F10 RISBGZ $32, $47, $0, R3, R4 RISBGZ $57, $60, $51, R3, R3 BYTE $0x18 //lr %r2,%r4 BYTE $0x24 RISBGN $0, $31, $32, R4, R1 SUBW $0x100000, R2 SRAW $8, R2, R2 ORW $0x45000000, R2 L5: LDGR R1, F0 FMOVD 104(R9), F2 FMADD F8, F0, F2 FMOVD 96(R9), F4 WFMADB V10, V0, V2, V0 FMOVD 88(R9), F6 FMOVD 80(R9), F2 WFMADB V0, V6, V4, V6 FMOVD 72(R9), F1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 4.3K bytes - Viewed (0) -
src/math/pow_s390x.s
BYTE $0x00 BYTE $0x90 SUBW $0x1A0000, R5 SLD $3, R0, R3 MOVD $·powtm<>+0(SB), R4 MOVH $0x0, R8 ANDW $0x7FF00000, R2 ORW R5, R1 WORD $0x5A234000 //a %r2,0(%r3,%r4) MOVD $0x3FF0000000000000, R5 RISBGZ $40, $63, $56, R2, R3 RISBGN $0, $31, $32, R2, R8 ORW $0x45000000, R3 MOVW R1, R6 CMPBLT R6, $0, L42 FMOVD F0, F4 L2: VLVGF $0, R3, V1 MOVD $·pow_xa<>+0(SB), R2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 16.3K bytes - Viewed (0) -
src/math/asinh_s390x.s
SRAD $32, R5 MOVH $0x0, R2 SUBW R5, R3 FMOVD $0, F8 RISBGZ $32, $47, $0, R3, R4 BYTE $0x18 //lr %r1,%r4 BYTE $0x14 RISBGN $0, $31, $32, R4, R2 SUBW $0x100000, R1 SRAW $8, R1, R1 ORW $0x45000000, R1 BR L6 L2: MOVD $0x30000000, R2 CMPW R1, R2 BGT L16 FMOVD 200(R9), F2 FMADD F2, F0, F0 L1: FMOVD F0, ret+8(FP) RET L14: LTDBR F0, F0 BLTU L17
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 15:34:41 UTC 2019 - 5.7K bytes - Viewed (0) -
src/math/atanh_s390x.s
FMOVD 48(R5), F5 WFMADB V4, V5, V3, V4 FMOVD 40(R5), F3 FMADD F1, F6, F4 FMOVD 32(R5), F1 FMADD F3, F2, F1 ANDW $0xFFFFFF00, R1 WFMADB V6, V4, V1, V6 FMOVD 24(R5), F3 ORW $0x45000000, R1 WFMADB V2, V6, V3, V6 VLVGF $0, R1, V4 LDEBR F4, F4 RISBGZ $57, $60, $51, R2, R2 MOVD $·atanhtab2076<>+0(SB), R1 FMOVD 16(R5), F3 WORD $0x68521000 //ld %f5,0(%r2,%r1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
"MOVW", "MOVWZ", "MOVD", "MOVDBR", "MOVDEQ", "MOVDGE", "MOVDGT", "MOVDLE", "MOVDLT", "MOVDNE", "LOCR", "LOCGR", "FLOGR", "POPCNT", "AND", "ANDW", "OR", "ORW", "XOR", "XORW", "SLW", "SLD", "SRW", "SRAW", "SRD", "SRAD", "RLL", "RLLG", "RNSBG", "RXSBG", "ROSBG", "RNSBGT", "RXSBGT", "ROSBGT", "RISBG", "RISBGN",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_s390x.s
MOVBZ val+8(FP), R4 // We don't have atomic operations that work on individual bytes so we // need to align addr down to a word boundary and create a mask // containing v to AND with the entire word atomically. ORW $~0xff, R4 // R4 = uint32(v) | 0xffffff00 MOVD $(3<<3), R5 RXSBG $59, $60, $3, R3, R5 // R5 = 24 - ((addr % 4) * 8) = ((addr & 3) << 3) ^ (3 << 3) ANDW $~3, R3 // R3 = floor(addr, 4) = addr &^ 3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 7.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0)