"NEGV",
	"NOR",
	"NORCC",
	"OR",
	"ORCC",
	"ORN",
	"ORNCC",
	"ORIS",
	"REM",
	"REMU",
	"RFI",
	"RLWMI",
	"RLWMICC",
	"RLWNM",
	"RLWNMCC",
	"CLRLSLWI",
	"SLW",
	"SLWCC",
	"SRW",
	"SRAW",
	"SRAWCC",
	"SRWCC",
	"STBCCC",
	"STHCCC",
	"STSW",
	"STWCCC",
	"SUB",
	"SUBCC",
	"SUBVCC",
	"SUBC",
	"SUBCCC",
	"SUBCV",
	"SUBCVCC",

	"MOVDBR",
	"MOVDEQ",
	"MOVDGE",
	"MOVDGT",
	"MOVDLE",
	"MOVDLT",
	"MOVDNE",
	"LOCR",
	"LOCGR",
	"FLOGR",
	"POPCNT",
	"AND",
	"ANDW",
	"OR",
	"ORW",
	"XOR",
	"XORW",
	"SLW",
	"SLD",
	"SRW",
	"SRAW",
	"SRD",
	"SRAD",
	"RLL",
	"RLLG",
	"RNSBG",
	"RXSBG",
	"ROSBG",
	"RNSBGT",
	"RXSBGT",
	"ROSBGT",
	"RISBG",
	"RISBGN",
	"RISBGZ",
	"RISBGNZ",

	FMOVD	56(R9), F1
	FMOVD	48(R9), F5
	WORD	$0xEC23393B	//rosbg	%r2,%r3,57,59,4
	BYTE	$0x04
	BYTE	$0x56
	WORD	$0xE3121000	//llc	%r1,0(%r2,%r1)
	BYTE	$0x00
	BYTE	$0x94
	ADDW	R3, R1
	ADDW	R4, R1
	SLW	$16, R1, R1
	SLD	$32, R1, R1
	LDGR	R1, F2
	WFMDB	V2, V2, V4
	WFMDB	V4, V0, V6
	WFMSDB	V4, V6, V2, V4
	FMOVD	40(R9), F6
	FMSUB	F1, F4, F2
	FMOVD	32(R9), F4
	WFMDB	V2, V2, V3
	FMOVD	24(R9), F1

		v.AddArg2(x, y)
		return true
	}
	// match: (SLW x (MOVWreg y))
	// result: (SLW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSLW)
		v.AddArg2(x, y)
		return true
	}
	// match: (SLW x (MOVHreg y))
	// result: (SLW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

	SRD	$4, R4, R7              // eb740004000c
	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de
	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a

// Lower bounded shifts first. No need to check shift value.
(Lsh64x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLD x y)
(Lsh32x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLW x y)
(Lsh16x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLW x y)
(Lsh8x(64|32|16|8)   x y) && shiftIsBounded(v) => (SLW x y)
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)

		return true
	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
		return true
	case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC:
		return true
	case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
		return true
	}
	return false
}

// revCondMap maps a conditional register bit to its inverse, if possible.

	// containing v to OR with the entire word atomically.
	MOVD	$(3<<3), R5
	RXSBG	$59, $60, $3, R3, R5 // R5 = 24 - ((addr % 4) * 8) = ((addr & 3) << 3) ^ (3 << 3)
	ANDW	$~3, R3              // R3 = floor(addr, 4) = addr &^ 3
	SLW	R5, R4               // R4 = uint32(v) << R5
	LAO	R4, R6, 0(R3)        // R6 = *R3; *R3 |= R4; (atomic)
	RET

// func And8(addr *uint8, v uint8)
TEXT ·And8(SB), NOSPLIT, $0-9
	MOVD	ptr+0(FP), R3

		{name: "SRW", argLength: 2, reg: gp21, asm: "SRW"},       // unsigned arg0 >> (arg1&63), 32 bit width
		{name: "SLD", argLength: 2, reg: gp21, asm: "SLD"},       // arg0 << (arg1&127), 64 bit width
		{name: "SLW", argLength: 2, reg: gp21, asm: "SLW"},       // arg0 << (arg1&63), 32 bit width

		{name: "ROTL", argLength: 2, reg: gp21, asm: "ROTL"},   // arg0 rotate left by arg1 mod 64

	return int64(v) >> 16
}

func rshConst64x64Overflow8(v int8) int64 {
	// riscv64:"SLLI","SRAI",-"SRAIW"
	return int64(v) >> 8
}

func lshConst32x64(v int32) int32 {
	// ppc64x:"SLW"
	// riscv64:"SLLI",-"AND",-"SLTIU", -"MOVW"
	return v << uint64(29)
}

func rshConst32Ux64(v uint32) uint32 {
	// ppc64x:"SRW"
	// riscv64:"SRLIW",-"AND",-"SLTIU", -"MOVW"
	return v >> uint64(29)
}