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Results 1 - 10 of 11 for SRAI (0.05 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64latelower.rules

    // license that can be found in the LICENSE file.
    
    // Fold constant shift with extension.
    (SRAI [c] (MOVBreg  x)) && c <   8 => (SRAI [56+c] (SLLI <typ.Int64> [56] x))
    (SRAI [c] (MOVHreg  x)) && c <  16 => (SRAI [48+c] (SLLI <typ.Int64> [48] x))
    (SRAI [c] (MOVWreg  x)) && c <  32 => (SRAI [32+c] (SLLI <typ.Int64> [32] x))
    (SRLI [c] (MOVBUreg x)) && c <   8 => (SRLI [56+c] (SLLI <typ.UInt64> [56] x))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Oct 24 03:45:10 UTC 2022
    - 980 bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteRISCV64latelower.go

    		return true
    	}
    	return false
    }
    func rewriteValueRISCV64latelower_OpRISCV64SRAI(v *Value) bool {
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (SRAI [c] (MOVBreg x))
    	// cond: c < 8
    	// result: (SRAI [56+c] (SLLI <typ.Int64> [56] x))
    	for {
    		c := auxIntToInt64(v.AuxInt)
    		if v_0.Op != OpRISCV64MOVBreg {
    			break
    		}
    		x := v_0.Args[0]
    		if !(c < 8) {
    			break
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jan 19 22:42:34 UTC 2023
    - 5.1K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 2.8K bytes
    - Viewed (0)
  4. test/codegen/shift.go

    	// ppc64x:"SRAD"
    	// riscv64:"SRAI\t",-"OR",-"SLTIU"
    	return v >> uint64(33)
    }
    
    func rshConst64x64Overflow32(v int32) int64 {
    	// riscv64:"SRAIW",-"SLLI",-"SRAI\t"
    	return int64(v) >> 32
    }
    
    func rshConst64x64Overflow16(v int16) int64 {
    	// riscv64:"SLLI","SRAI",-"SRAIW"
    	return int64(v) >> 16
    }
    
    func rshConst64x64Overflow8(v int8) int64 {
    	// riscv64:"SLLI","SRAI",-"SRAIW"
    	return int64(v) >> 8
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (SRAI <t> [x] (MOVWreg  y)) && x >= 0 && x <= 31 => (SRAIW <t> [int64(x)] y)
    (SRLI <t> [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW <t> [int64(x)] y)
    
    // Replace right shifts that exceed size of signed type.
    (SRAI <t> [x] (MOVBreg y)) && x >=  8 => (SRAI  [63] (SLLI <t> [56] y))
    (SRAI <t> [x] (MOVHreg y)) && x >= 16 => (SRAI  [63] (SLLI <t> [48] y))
    (SRAI <t> [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/riscv/anames.go

    package riscv
    
    import "cmd/internal/obj"
    
    var Anames = []string{
    	obj.A_ARCHSPECIFIC: "ADDI",
    	"SLTI",
    	"SLTIU",
    	"ANDI",
    	"ORI",
    	"XORI",
    	"SLLI",
    	"SRLI",
    	"SRAI",
    	"LUI",
    	"AUIPC",
    	"ADD",
    	"SLT",
    	"SLTU",
    	"AND",
    	"OR",
    	"XOR",
    	"SLL",
    	"SRL",
    	"SUB",
    	"SRA",
    	"JAL",
    	"JALR",
    	"BEQ",
    	"BNE",
    	"BLT",
    	"BLTU",
    	"BGE",
    	"BGEU",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/riscv64.s

    	XORI	$1, X5					// 93c21200
    	XORI	$2048, X5				// b71f00009b8f0f80b3c2f201
    
    	SLLI	$1, X5, X6				// 13931200
    	SLLI	$1, X5					// 93921200
    	SRLI	$1, X5, X6				// 13d31200
    	SRLI	$1, X5					// 93d21200
    	SRAI	$1, X5, X6				// 13d31240
    	SRAI	$1, X5					// 93d21240
    
    	ADD	X6, X5, X7				// b3836200
    	ADD	X5, X6					// 33035300
    	ADD	$2047, X5, X6				// 1383f27f
    	ADD	$-2048, X5, X6				// 13830280
    	ADD	$2047, X5				// 9382f27f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "SLLIW", argLength: 1, reg: gp11, asm: "SLLIW", aux: "Int64"}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, sign extended to 64 bits
    		{name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, arithmetic right shift
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		}
    		v.reset(OpRISCV64SRAIW)
    		v.Type = t
    		v.AuxInt = int64ToAuxInt(int64(x))
    		v.AddArg(y)
    		return true
    	}
    	// match: (SRAI <t> [x] (MOVBreg y))
    	// cond: x >= 8
    	// result: (SRAI [63] (SLLI <t> [56] y))
    	for {
    		t := v.Type
    		x := auxIntToInt64(v.AuxInt)
    		if v_0.Op != OpRISCV64MOVBreg {
    			break
    		}
    		y := v_0.Args[0]
    		if !(x >= 8) {
    			break
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/riscv/obj.go

    				// Use SEXTB or SEXTH to extend.
    				ins.as, ins.rs1, ins.rs2 = ASEXTB, uint32(p.From.Reg), obj.REG_NONE
    				if p.As == AMOVH {
    					ins.as = ASEXTH
    				}
    			} else {
    				// Use SLLI/SRAI sequence to extend.
    				ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
    				if p.As == AMOVB {
    					ins.imm = 56
    				} else if p.As == AMOVH {
    					ins.imm = 48
    				}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
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