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Results 1 - 10 of 29 for ADDI (1.06 sec)
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src/cmd/asm/internal/asm/testdata/riscv64.s
// 2.4: Integer Computational Instructions ADDI $2047, X5 // 9382f27f ADDI $-2048, X5 // 93820280 ADDI $2048, X5 // 9382024093820240 ADDI $-2049, X5 // 938202c09382f2bf ADDI $4094, X5 // 9382f27f9382f27f ADDI $-4096, X5 // 9382028093820280 ADDI $4095, X5 // b71f00009b8fffffb382f201 ADDI $-4097, X5 // b7ffffff9b8fffffb382f201 ADDI $2047, X5, X6 // 1383f27f ADDI $-2048, X5, X6 // 13830280
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/runtime/cgo/gcc_riscv64.S
* Called from standard RISCV ELF psABI, where x8-x9, x18-x27, f8-f9 and * f18-f27 are callee-save, so they must be saved explicitly, along with * x1 (LR). */ .globl crosscall1 crosscall1: sd x1, -200(sp) addi sp, sp, -200 sd x8, 8(sp) sd x9, 16(sp) sd x18, 24(sp) sd x19, 32(sp) sd x20, 40(sp) sd x21, 48(sp) sd x22, 56(sp) sd x23, 64(sp) sd x24, 72(sp) sd x25, 80(sp) sd x26, 88(sp)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Dec 05 16:41:48 UTC 2022 - 1.6K bytes - Viewed (0) -
src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S
.type toc_func, @function toc_func: addis 2,12,.TOC.-toc_func@ha addi 2,2,.TOC.-toc_func@l .localentry toc_func, .-toc_func mflr 0 std 0,16(1) stdu 1,-32(1) // Call a NOTOC function which clobbers R2. bl notoc_nor2_func nop // Call libc random. This should generate a TOC relative plt stub. bl random nop addi 1,1,32 ld 0,16(1) mtlr 0 blr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Sep 22 15:06:17 UTC 2023 - 3.7K bytes - Viewed (0) -
src/runtime/cgo/gcc_loong64.S
* Called from standard lp64d ABI, where $r1, $r3, $r23-$r30, and $f24-$f31 * are callee-save, so they must be saved explicitly, along with $r1 (LR). */ .globl crosscall1 crosscall1: addi.d $r3, $r3, -160 st.d $r1, $r3, 0 st.d $r23, $r3, 8 st.d $r24, $r3, 16 st.d $r25, $r3, 24 st.d $r26, $r3, 32 st.d $r27, $r3, 40 st.d $r28, $r3, 48 st.d $r29, $r3, 56 st.d $r30, $r3, 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Dec 05 18:57:04 UTC 2022 - 1.5K bytes - Viewed (0) -
src/cmd/link/internal/ppc64/asm.go
if target.IsAIX() && rt == objabi.R_POWER_TLS_LE { // Fixup val, an addis/addi pair of instructions, which generate a 32b displacement // from the threadpointer (R13), into a 16b relocation. XCOFF only supports 16b // TLS LE relocations. Likewise, verify this is an addis/addi sequence. const expectedOpcodes = 0x3C00000038000000 const expectedOpmasks = 0xFC000000FC000000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 19 20:54:08 UTC 2024 - 63.7K bytes - Viewed (0) -
src/cmd/link/internal/loong64/asm.go
// 0: R_LARCH_PCALA_HI20 local.moduledata o(0x1a000004) rel, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_HI) rel.SetOff(0) rel.SetSiz(4) rel.SetSym(ctxt.Moduledata) // 4: 02c00084 addi.d $a0, $a0, 0 // 4: R_LARCH_PCALA_LO12 local.moduledata o(0x02c00084) rel2, _ := initfunc.AddRel(objabi.R_LOONG64_ADDR_LO) rel2.SetOff(4) rel2.SetSiz(4) rel2.SetSym(ctxt.Moduledata) // 8: 50000000 b 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Feb 27 17:26:07 UTC 2024 - 7.5K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
// Code generated by stringer -i cpu.go -o anames.go -p riscv; DO NOT EDIT. package riscv import "cmd/internal/obj" var Anames = []string{ obj.A_ARCHSPECIFIC: "ADDI", "SLTI", "SLTIU", "ANDI", "ORI", "XORI", "SLLI", "SRLI", "SRAI", "LUI", "AUIPC", "ADD", "SLT", "SLTU", "AND", "OR", "XOR", "SLL", "SRL", "SUB", "SRA", "JAL", "JALR", "BEQ", "BNE",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/g3doc/_index.yaml
// Syntactically similar to LLVM: func @testFunction(%arg0: i32) { %x = call @thingToCall(%arg0) : (i32) -> i32 br ^bb1 ^bb1: %y = arith.addi %x, %x : i32 return %y : i32 } </pre> - classname: devsite-landing-row-cards items: - heading: "Multi-Level Intermediate Representation for Compiler Infrastructure"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Oct 13 16:33:28 UTC 2021 - 2.4K bytes - Viewed (0) -
src/runtime/cgo/gcc_linux_ppc64x.S
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 04 18:03:04 UTC 2023 - 2K bytes - Viewed (0)