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// Code generated by stringer -i cpu.go -o anames.go -p riscv; DO NOT EDIT.

package riscv

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADDI",
	"SLTI",
	"SLTIU",
	"ANDI",
	"ORI",
	"XORI",
	"SLLI",
	"SRLI",
	"SRAI",
	"LUI",
	"AUIPC",
	"ADD",
	"SLT",
	"SLTU",
	"AND",
	"OR",
	"XOR",
	"SLL",
	"SRL",
	"SUB",
	"SRA",
	"JAL",
	"JALR",
	"BEQ",
	"BNE",

(ANDI [x] (MOVDconst [y])) => (MOVDconst [x & y])

// ORI with all zeroes, all ones or two constants.
(ORI [0]  x) => x
(ORI [-1] x) => (MOVDconst [-1])
(ORI [x] (MOVDconst [y])) => (MOVDconst [x | y])

// Combine operations with immediate.
(ADDI [x] (ADDI [y] z)) && is32Bit(x + y) => (ADDI [x + y] z)
(ANDI [x] (ANDI [y] z)) => (ANDI [x & y] z)
(ORI  [x] (ORI  [y] z)) => (ORI  [x | y] z)

// Negation of a constant.

	SLTI	$55, X5, X7				// 93a37203
	SLTIU	$55, X5, X7				// 93b37203

	ANDI	$1, X5, X6				// 13f31200
	ANDI	$1, X5					// 93f21200
	ANDI	$2048, X5				// b71f00009b8f0f80b3f2f201
	ORI	$1, X5, X6				// 13e31200
	ORI	$1, X5					// 93e21200
	ORI	$2048, X5				// b71f00009b8f0f80b3e2f201
	XORI	$1, X5, X6				// 13c31200
	XORI	$1, X5					// 93c21200
	XORI	$2048, X5				// b71f00009b8f0f80b3c2f201

	SLLI	$1, X5, X6				// 13931200

	LHZX:      "MOVHZ",
	LHZUX:     "MOVHZU",
	LBZX:      "MOVBZ",
	LBZUX:     "MOVBZU",
	LDBRX:     "MOVDBR",
	LWBRX:     "MOVWBR",
	LHBRX:     "MOVHBR",
	MCRF:      "MOVFL",
	XORI:      "XOR",
	ORI:       "OR",
	ANDICC:    "ANDCC",
	ANDC:      "ANDN",
	ANDCCC:    "ANDNCC",
	ADDEO:     "ADDEV",
	ADDEOCC:   "ADDEVCC",
	ADDO:      "ADDV",
	ADDOCC:    "ADDVCC",
	ADDMEO:    "ADDMEV",

		o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
		o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)

	case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add, add $s34con,r1 ==> addis+ori+slw+ori+add */
		if p.To.Reg == REGTMP || p.Reg == REGTMP {
			c.ctxt.Diag("can't synthesize large constant\n%v", p)
		}
		d := c.vregoff(&p.From)
		r := int(p.Reg)
		if r == 0 {

		{name: "NOT", argLength: 1, reg: gp11, asm: "NOT"},                    // ^arg0
		{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},   // arg0 | arg1
		{name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"},      // arg0 | auxint
		{name: "ROL", argLength: 2, reg: gp21, asm: "ROL"},                    // rotate left arg0 by (arg1 & 63)

		rel2.Off = int32(c.pc + 4)
		rel2.Siz = 4
		rel2.Sym = p.From.Sym
		rel2.Add = p.From.Offset
		rel2.Type = objabi.R_LOONG64_ADDR_LO

	case 53: // mov r, tlsvar ==>  lu12i.w + ori + add r2, regtmp + sw o(regtmp)
		// NOTE: this case does not use REGTMP. If it ever does,
		// remove the NOTUSETMP flag in optab.
		o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
		rel := obj.Addrel(c.cursym)

ṣe'dúró fún **FastAPI**. Ó jẹ́ ohun tí **àgbékalẹ̀ rẹ̀ lẹ́wà**, **ó rọrùn láti lò** àti wipe ó ni **ìwọ̀n gíga**, o tí dí **bọtini paati** nínú alakọkọ API ìdàgbàsókè kikọ fún wa, àti pe o ni ipa lori adaṣiṣẹ àti àwọn iṣẹ gẹ́gẹ́ bíi Onímọ̀-ẹ̀rọ TAC tí órí Íńtánẹ́ẹ̀tì_"

<div style="text-align: right; margin-right: 10%;">Deon Pillsbury - <strong>Cisco</strong> <a href="https://www.linkedin.com/posts/deonpillsbury_cisco-cx-python-activity-6963242628536487936-trAp/" target="_blank"><small>(re...

		return true
	}
	// match: (ORI [x] (MOVDconst [y]))
	// result: (MOVDconst [x | y])
	for {
		x := auxIntToInt64(v.AuxInt)
		if v_0.Op != OpRISCV64MOVDconst {
			break
		}
		y := auxIntToInt64(v_0.AuxInt)
		v.reset(OpRISCV64MOVDconst)
		v.AuxInt = int64ToAuxInt(x | y)
		return true
	}
	// match: (ORI [x] (ORI [y] z))
	// result: (ORI [x | y] z)
	for {