Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 24 for is32Bit (0.15 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (MOVHUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
    (MOVHUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
    (MOVHloadidx  ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHload  [int32(c)] ptr mem)
    (MOVHloadidx  (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHload  [int32(c)] ptr mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    	v_0 := v.Args[0]
    	// match: (ADDV x (MOVVconst <t> [c]))
    	// cond: is32Bit(c) && !t.IsPtr()
    	// result: (ADDVconst [c] x)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpLOONG64MOVVconst {
    				continue
    			}
    			t := v_1.Type
    			c := auxIntToInt64(v_1.AuxInt)
    			if !(is32Bit(c) && !t.IsPtr()) {
    				continue
    			}
    			v.reset(OpLOONG64ADDVconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    // fold constant into arithmetic ops
    (ADDV x (MOVVconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDVconst [c] x)
    (SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
    (AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
    (OR  x (MOVVconst [c])) && is32Bit(c) => (ORconst  [c] x)
    (XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
    (NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    	(MOVHUload [off1+int32(off2)] {sym} base mem)
    (MOVHload  [off1] {sym} (ADDI [off2] base) mem) && is32Bit(int64(off1)+off2) =>
    	(MOVHload  [off1+int32(off2)] {sym} base mem)
    (MOVWUload [off1] {sym} (ADDI [off2] base) mem) && is32Bit(int64(off1)+off2) =>
    	(MOVWUload [off1+int32(off2)] {sym} base mem)
    (MOVWload  [off1] {sym} (ADDI [off2] base) mem) && is32Bit(int64(off1)+off2) =>
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (ADD(Q|L)const [c] (LEA(Q|L)1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)1 [c+d] {s} x y)
    (ADD(Q|L)const [c] (LEA(Q|L)2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)2 [c+d] {s} x y)
    (ADD(Q|L)const [c] (LEA(Q|L)4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)4 [c+d] {s} x y)
    (ADD(Q|L)const [c] (LEA(Q|L)8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)8 [c+d] {s} x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    // fold constant into arithmetic ops
    (ADDV x (MOVVconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDVconst [c] x)
    (SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
    (AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
    (OR  x (MOVVconst [c])) && is32Bit(c) => (ORconst  [c] x)
    (XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
    (NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/rewrite386.go

    		v.AddArg2(x, y)
    		return true
    	}
    	// match: (ADDLconst [c] (LEAL [d] {s} x))
    	// cond: is32Bit(int64(c)+int64(d))
    	// result: (LEAL [c+d] {s} x)
    	for {
    		c := auxIntToInt32(v.AuxInt)
    		if v_0.Op != Op386LEAL {
    			break
    		}
    		d := auxIntToInt32(v_0.AuxInt)
    		s := auxToSym(v_0.Aux)
    		x := v_0.Args[0]
    		if !(is32Bit(int64(c) + int64(d))) {
    			break
    		}
    		v.reset(Op386LEAL)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 21:05:46 UTC 2023
    - 262.4K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewriteAMD64.go

    	v_0 := v.Args[0]
    	// match: (ADCQ x (MOVQconst [c]) carry)
    	// cond: is32Bit(c)
    	// result: (ADCQconst x [int32(c)] carry)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpAMD64MOVQconst {
    				continue
    			}
    			c := auxIntToInt64(v_1.AuxInt)
    			carry := v_2
    			if !(is32Bit(c)) {
    				continue
    			}
    			v.reset(OpAMD64ADCQconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteMIPS64.go

    	v_0 := v.Args[0]
    	// match: (ADDV x (MOVVconst <t> [c]))
    	// cond: is32Bit(c) && !t.IsPtr()
    	// result: (ADDVconst [c] x)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpMIPS64MOVVconst {
    				continue
    			}
    			t := v_1.Type
    			c := auxIntToInt64(v_1.AuxInt)
    			if !(is32Bit(c) && !t.IsPtr()) {
    				continue
    			}
    			v.reset(OpMIPS64ADDVconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 211.6K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (CGRJ  {c} x (MOVDconst [y]) yes no) && !is8Bit(y)  && is32Bit(y)  => (BRC {c} (CMPconst   x [int32(y)]) yes no)
    (CRJ   {c} x (MOVDconst [y]) yes no) && !is8Bit(y)  && is32Bit(y)  => (BRC {c} (CMPWconst  x [int32(y)]) yes no)
    (CLGRJ {c} x (MOVDconst [y]) yes no) && !isU8Bit(y) && isU32Bit(y) => (BRC {c} (CMPUconst  x [int32(y)]) yes no)
    (CLRJ  {c} x (MOVDconst [y]) yes no) && !isU8Bit(y) && isU32Bit(y) => (BRC {c} (CMPWUconst x [int32(y)]) yes no)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
Back to top