check:
	ANDCC $7, R4, R5  // R5: leftover bytes to clear
	SRD   $3, R4, R6  // R6: double words to clear
	CMP   R6, $0, CR1 // CR1[EQ] set if no double words

	BC    12, 6, nozerolarge // only single bytes
	CMP   R4, $512
	BLT   under512           // special case for < 512
	ANDCC $127, R3, R8       // check for 128 alignment of address
	BEQ   zero512setup

	ANDCC $7, R3, R15

	VADDUDM	V2, V5, V5	// The count will be fixed up afterwards.
	ADD	$32, R3
	BDNZ	cmploop

	VADDUDM	V4, V5, V5
	MFVSRD	V5, R18
	VSLDOI	$8, V5, V5, V5
	MFVSRD	V5, R21
	ADD	R21, R18, R18
	ANDCC	$31, R4, R4
	// Skip the tail processing if no bytes remaining.
	BEQ	tail_0

#ifdef GOPPC64_power10
	SRD	$3, R18, R18	// Fix the vector loop count before counting the tail on P10.

tail:	// Count the last 0 - 31 bytes.

	// Truncate not needed, load does sign/zero extend

	// ppc64x:-"MOVBZ\tR\\d+,\\sR\\d+"
	val16[0] = uint16(*u8)

	// AND not needed due to size
	// ppc64x:-"ANDCC"
	sval16[1] = 255 & int16(x8+y8)

	// ppc64x:-"ANDCC"
	val16[1] = 255 & uint16(*u8+z8)

}
func shiftidx(u8 *uint8, x16 *int16, u16 *uint16) {

	// ppc64x:-"MOVBZ\tR\\d+,\\sR\\d+"
	val16[0] = uint16(sval16[*u8>>2])

	RET

	PCALIGN	$16
cmp4:	// 4 - 7B
	CMP	R9,$4
	BLT	cmp2
	ANDCC	$3,R9,R9
	_LWBEX	(R0)(R5),R10
	_LWBEX	(R0)(R6),R11
	_LWBEX	(R9)(R5),R12
	_LWBEX	(R9)(R6),R14
	RLDIMI	$32,R10,$0,R12
	RLDIMI	$32,R11,$0,R14
	CMPU	R12,R14
	BR	cmp0

	PCALIGN $16
cmp2:	// 2 - 3B
	CMP	R9,$2
	BLT	cmp1
	ANDCC	$1,R9,R9
	_LHBEX	(R0)(R5),R10
	_LHBEX	(R0)(R6),R11
	_LHBEX	(R9)(R5),R12

check:
#ifdef GOPPC64_power10
	CMP	LEN, $16
	BGT	mcopy
	SLD	$56, LEN, TMP
	LXVL	SRC, TMP, V0
	STXVL	V0, TGT, TMP
	RET
#endif
mcopy:
	ANDCC	$7, LEN, BYTES	// R7: bytes to copy
	SRD	$3, LEN, DWORDS	// R6: double words to copy
	MOVFL	CR0, CR3	// save CR from ANDCC
	CMP	DWORDS, $0, CR1	// CR1[EQ] set if no double words to copy

	// Determine overlap by subtracting dest - src and comparing against the

func signextendAndMask8to64(a int8) (s, z uint64) {
	// ppc64x: "MOVB", "ANDCC\t[$]1015,"
	s = uint64(a) & 0x3F7
	// ppc64x: -"MOVB", "ANDCC\t[$]247,"
	z = uint64(uint8(a)) & 0x3F7
	return
}

// Verify zero-extended values are not sign-extended under a bit mask (#61297)
func zeroextendAndMask8to64(a int8, b int16) (x, y uint64) {
	// ppc64x: -"MOVB\t", -"ANDCC", "MOVBZ"
	x = uint64(a) & 0xFF

	ADDIS $1000, R3, R4             // 3c8303e8

	ANDCC $1, R3                    // 70630001
	ANDCC $1, R3, R4                // 70640001
	ANDCC $-1, R4                   // 3be0ffff7fe42039
	ANDCC $-1, R4, R5               // 3be0ffff7fe52039
	ANDCC $65535, R5                // 70a5ffff
	ANDCC $65535, R5, R6            // 70a6ffff
	ANDCC $65536, R6                // 74c60001
	ANDCC $65536, R6, R7            // 74c70001

	// extra bytes from the higher addresses. And align those values
	// consistently in register as either address may have differing
	// alignment requirements.
	ANDCC	$PAGE_OFFSET, R8, R6	// &sX & PAGE_OFFSET
	ANDCC	$PAGE_OFFSET, R4, R9
	SUBC	R5, $8, R12		// 8-len
	SLD	$3, R12, R14		// (8-len)*8
	CMPU	R6, R12, CR1		// Enough bytes lower in the page to load lower?
	CMPU	R9, R12, CR0

	BLT	cmp1

	_LHBEX	(R0)(R3),R10
	CMPB	R10,R5,R10
	SLDCC	$48,R10,R10
	CNTLZD	R10,R10
	SRD	$3,R10,R3
	BNE	found

cmp1:	// Length 1
	MOVD	$-1,R3
	ANDCC	$1,R4,R31
	BEQ	found

	MOVBZ	-1(R9),R10
	CMPB	R10,R5,R10
	ANDCC	$1,R10
	ADD	$-1,R4
	ISEL	CR0EQ,R3,R4,R3

found:
	RET
#endif

notfound:
	MOVD $-1,R3

		return true
	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
		return true
	case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC:
		return true
	case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
		return true
	}
	return false
}