return true
	}
	return false
}
func rewriteValueRISCV64latelower_OpRISCV64SRLI(v *Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SRLI [c] (MOVBUreg x))
	// cond: c < 8
	// result: (SRLI [56+c] (SLLI <typ.UInt64> [56] x))
	for {
		c := auxIntToInt64(v.AuxInt)
		if v_0.Op != OpRISCV64MOVBUreg {
			break
		}
		x := v_0.Args[0]
		if !(c < 8) {
			break
		}

(SRLI [c] (MOVBUreg x)) && c <   8 => (SRLI [56+c] (SLLI <typ.UInt64> [56] x))
(SRLI [c] (MOVHUreg x)) && c <  16 => (SRLI [48+c] (SLLI <typ.UInt64> [48] x))
(SRLI [c] (MOVWUreg x)) && c <  32 => (SRLI [32+c] (SLLI <typ.UInt64> [32] x))
(SLLI [c] (MOVBUreg x)) && c <= 56 => (SRLI [56-c] (SLLI <typ.UInt64> [56] x))
(SLLI [c] (MOVHUreg x)) && c <= 48 => (SRLI [48-c] (SLLI <typ.UInt64> [48] x))

	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"

	// amd64:"ROLW\t[$]7"
	// riscv64: "OR","SLLI","SRLI",-"AND"
	a += x<<7 | x>>9

	// amd64:`ROLW\t[$]8`
	// riscv64: "OR","SLLI","SRLI",-"AND"
	a += x<<8 + x>>8

	// amd64:"ROLW\t[$]9"
	// riscv64: "OR","SLLI","SRLI",-"AND"
	a += x<<9 ^ x>>7

	return a
}

func rot8(x uint8) uint8 {
	var a uint8

	// amd64:"ROLB\t[$]5"
	// riscv64: "OR","SLLI","SRLI",-"AND"
	a += x<<5 | x>>3

(SRAI <t> [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)

// Eliminate right shifts that exceed size of unsigned type.
(SRLI <t> [x] (MOVBUreg y)) && x >=  8 => (MOVDconst <t> [0])
(SRLI <t> [x] (MOVHUreg y)) && x >= 16 => (MOVDconst <t> [0])
(SRLI <t> [x] (MOVWUreg y)) && x >= 32 => (MOVDconst <t> [0])

// Fold constant into immediate instructions where possible.

package riscv

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADDI",
	"SLTI",
	"SLTIU",
	"ANDI",
	"ORI",
	"XORI",
	"SLLI",
	"SRLI",
	"SRAI",
	"LUI",
	"AUIPC",
	"ADD",
	"SLT",
	"SLTU",
	"AND",
	"OR",
	"XOR",
	"SLL",
	"SRL",
	"SUB",
	"SRA",
	"JAL",
	"JALR",
	"BEQ",
	"BNE",
	"BLT",
	"BLTU",
	"BGE",

	XORI	$1, X5, X6				// 13c31200
	XORI	$1, X5					// 93c21200
	XORI	$2048, X5				// b71f00009b8f0f80b3c2f201

	SLLI	$1, X5, X6				// 13931200
	SLLI	$1, X5					// 93921200
	SRLI	$1, X5, X6				// 13d31200
	SRLI	$1, X5					// 93d21200
	SRAI	$1, X5, X6				// 13d31240
	SRAI	$1, X5					// 93d21240

	ADD	X6, X5, X7				// b3836200
	ADD	X5, X6					// 33035300
	ADD	$2047, X5, X6				// 1383f27f

// ------------------ //

func lshConst64x64(v int64) int64 {
	// ppc64x:"SLD"
	// riscv64:"SLLI",-"AND",-"SLTIU"
	return v << uint64(33)
}

func rshConst64Ux64(v uint64) uint64 {
	// ppc64x:"SRD"
	// riscv64:"SRLI\t",-"AND",-"SLTIU"
	return v >> uint64(33)
}

func rshConst64Ux64Overflow32(v uint32) uint64 {
	// riscv64:"MOV\t\\$0,",-"SRL"
	return uint64(v) >> 32
}

func rshConst64Ux64Overflow16(v uint16) uint64 {

		{name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits
		{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, logical right shift

	//      l[w|d] t3, %pcrel_lo(1b)(t2)    # _dl_runtime_resolve
	//      addi   t1, t1, -(hdr size + 12) # shifted .got.plt offset
	//      addi   t0, t2, %pcrel_lo(1b)    # &.got.plt
	//      srli   t1, t1, log2(16/PTRSIZE) # .got.plt offset
	//      l[w|d] t0, PTRSIZE(t0)          # link map
	//      jr     t3

	plt.AddSymRef(ctxt.Arch, gotplt.Sym(), 0, objabi.R_RISCV_PCREL_HI20, 4)