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samples/certs/generate-workload.sh
exit 1 fi fi function cleanup() { if [ -f "$FINAL_DIR"/.srl ]; then rm "$FINAL_DIR"/.srl fi if [ -f "$FINAL_DIR"/ca-cert.srl ]; then rm "$FINAL_DIR"/ca-cert.srl fi if [ -f "$FINAL_DIR"/ca-cert-alt.srl ]; then rm "$FINAL_DIR"/ca-cert-alt.srl fi if [ -f "$FINAL_DIR"/workload.cfg ]; then rm "$FINAL_DIR"/workload.cfg fi
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Tue Feb 07 23:57:35 UTC 2023 - 3.2K bytes - Viewed (0) -
test/codegen/shift.go
return v >> uint64(33) } func rshConst64Ux64Overflow32(v uint32) uint64 { // riscv64:"MOV\t\\$0,",-"SRL" return uint64(v) >> 32 } func rshConst64Ux64Overflow16(v uint16) uint64 { // riscv64:"MOV\t\\$0,",-"SRL" return uint64(v) >> 16 } func rshConst64Ux64Overflow8(v uint8) uint64 { // riscv64:"MOV\t\\$0,",-"SRL" return uint64(v) >> 8 } func rshConst64x64(v int64) int64 { // ppc64x:"SRAD"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
tools/certs/common.mk
#------------------------------------------------------------------------ # variables: files to clean FILES_TO_CLEAN+=k8s-root-cert.pem \ k8s-root-cert.srl \ k8s-root-key.pem root-ca.conf root-cert.csr root-cert.pem root-cert.srl root-key.pem #------------------------------------------------------------------------ # clean .PHONY: clean
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Mon Feb 20 08:51:56 UTC 2023 - 3.6K bytes - Viewed (0) -
test/codegen/rotate.go
z &= 15 // amd64:"ROLW",-"ANDQ" // riscv64: "OR","SLL","SRL",-"AND\t" a += x<<z | x>>(16-z) // amd64:"RORW",-"ANDQ" // riscv64: "OR","SLL","SRL",-"AND\t" a += x>>z | x<<(16-z) return a } func rot8nc(x uint8, z uint) uint8 { var a uint8 z &= 7 // amd64:"ROLB",-"ANDQ" // riscv64: "OR","SLL","SRL",-"AND\t" a += x<<z | x>>(8-z) // amd64:"RORB",-"ANDQ"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 6K bytes - Viewed (0) -
src/main/java/org/codelibs/fess/mylasta/direction/sponsor/FessListedClassificationProvider.java
//String searchName = classificationName; //if (classificationName.contains(".")) { // final String dbName = Srl.substringFirstFront(classificationName, "."); // if (dbName.equals(DBCurrent.getInstance().projectName())) { // searchName = Srl.substringFirstRear(classificationName, "."); // } else { // return null; // } //} //try {
Registered: Wed Jun 12 13:08:18 UTC 2024 - Last Modified: Thu Feb 22 01:37:57 UTC 2024 - 2.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(Rsh32Ux32 x y) => (CMOVWHSconst (SRL <x.Type> x y) (CMPconst [256] y) [0]) (Rsh32Ux16 x y) => (CMOVWHSconst (SRL <x.Type> x (ZeroExt16to32 y)) (CMPconst [256] (ZeroExt16to32 y)) [0]) (Rsh32Ux8 x y) => (SRL x (ZeroExt8to32 y)) (Rsh16Ux32 x y) => (CMOVWHSconst (SRL <x.Type> (ZeroExt16to32 x) y) (CMPconst [256] y) [0])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(Rsh8Ux32 <t> x y) && !shiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt32to64 y)))) (Rsh8Ux64 <t> x y) && !shiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] y))) (Rsh16Ux8 <t> x y) && !shiftIsBounded(v) => (AND (SRL <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
ADD R4, R5 // a5101000 ADDV R4, R5 // a5901000 AND R4, R5 // a5901400 NEGW R4, R5 // 05101100 NEGV R4, R5 // 05901100 SLL R4, R5 // a5101700 SLL R4, R5, R6 // a6101700 SRL R4, R5 // a5901700 SRL R4, R5, R6 // a6901700 SRA R4, R5 // a5101800 SRA R4, R5, R6 // a6101800 ROTR R4, R5 // a5101b00 ROTR R4, R5, R6 // a6101b00 SLLV R4, R5 // a5901800 SLLV R4, R5, R6 // a6901800
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
"NMULSD", "FMULAF", "FMULAD", "FNMULAF", "FNMULAD", "FMULSF", "FMULSD", "FNMULSF", "FNMULSD", "DIVF", "DIVD", "SQRTF", "SQRTD", "ABSF", "ABSD", "NEGF", "NEGD", "SRL", "SRA", "SLL", "MULU", "DIVU", "MUL", "MMUL", "DIV", "MOD", "MODU", "DIVHW", "DIVUHW", "MOVB", "MOVBS", "MOVBU", "MOVH", "MOVHS", "MOVHU", "MOVW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SRL.S $31, R5, R6 // a56fb0e1 SRL $14, R5 // 2557a0e1 SRL $15, R5 // a557a0e1 SRL $30, R5 // 255fa0e1 SRL $31, R5 // a55fa0e1 SRL.S $14, R5 // 2557b0e1 SRL.S $15, R5 // a557b0e1 SRL.S $30, R5 // 255fb0e1 SRL.S $31, R5 // a55fb0e1 SRL R5, R6, R7 // 3675a0e1 SRL.S R5, R6, R7 // 3675b0e1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0)