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Results 1 - 10 of 17 for ROLW (0.43 sec)

  1. test/fixedbugs/issue59367.go

    func f16(p *uint8, b []byte) {
    	_ = b[1]            // bounds check
    	x := *p             // load a byte
    	y := uint16(x)      // zero extend to 16 bits
    	b[0] = byte(y >> 8) // compute ROLW
    	b[1] = byte(y)
    	nop()               // spill/restore ROLW
    	b[0] = byte(y >> 8) // use ROLW
    	b[1] = byte(y)
    }
    
    //go:noinline
    func f32(p *uint8, b []byte) {
    	_ = b[3]             // bounds check
    	x := *p              // load a byte
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 07 21:11:29 UTC 2023
    - 1.7K bytes
    - Viewed (0)
  2. test/codegen/rotate.go

    	a += bits.RotateLeft32(x, 10)
    
    	return a
    }
    
    func rot16(x uint16) uint16 {
    	var a uint16
    
    	// amd64:"ROLW\t[$]7"
    	// riscv64: "OR","SLLI","SRLI",-"AND"
    	a += x<<7 | x>>9
    
    	// amd64:`ROLW\t[$]8`
    	// riscv64: "OR","SLLI","SRLI",-"AND"
    	a += x<<8 + x>>8
    
    	// amd64:"ROLW\t[$]9"
    	// riscv64: "OR","SLLI","SRLI",-"AND"
    	a += x<<9 ^ x>>7
    
    	return a
    }
    
    func rot8(x uint8) uint8 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 6K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/anames.go

    	"ANDN",
    	"ORN",
    	"XNOR",
    	"CLZ",
    	"CLZW",
    	"CTZ",
    	"CTZW",
    	"CPOP",
    	"CPOPW",
    	"MAX",
    	"MAXU",
    	"MIN",
    	"MINU",
    	"SEXTB",
    	"SEXTH",
    	"ZEXTH",
    	"ROL",
    	"ROLW",
    	"ROR",
    	"RORI",
    	"RORIW",
    	"RORW",
    	"ORCB",
    	"REV8",
    	"BCLR",
    	"BCLRI",
    	"BEXT",
    	"BEXTI",
    	"BINV",
    	"BINVI",
    	"BSET",
    	"BSETI",
    	"WORD",
    	"BEQZ",
    	"BGEZ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  4. test/codegen/memcombine.go

    }
    
    func store_be16(b []byte, x uint16) {
    	// amd64/v1,amd64/v2:`ROLW\s\$8`,-`SHR.`
    	// amd64/v3:`MOVBEW`,-`ROLW`
    	// arm64:`MOVH`,`REV16W`,-`MOVB`
    	// ppc64le:`MOVHBR`
    	// ppc64:`MOVH\s`
    	// s390x:`MOVH\s.*\(.*\)$`,-`SRW\s`,-`SRD\s`
    	binary.BigEndian.PutUint16(b, x)
    }
    
    func store_be16_idx(b []byte, x uint16, idx int) {
    	// amd64/v1,amd64/v2:`ROLW\s\$8`,-`SHR.`
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 21 19:45:41 UTC 2024
    - 29.7K bytes
    - Viewed (0)
  5. test/codegen/mathbits.go

    	// arm:`MOVW\tR[0-9]+@>23`
    	// arm64:"RORW"
    	// ppc64x:"ROTLW"
    	// s390x:"RLL"
    	// wasm:"I32Rotl"
    	return bits.RotateLeft32(n, 9)
    }
    
    func RotateLeft16(n uint16, s int) uint16 {
    	// amd64:"ROLW" 386:"ROLW"
    	// arm64:"RORW",-"CSEL"
    	return bits.RotateLeft16(n, s)
    }
    
    func RotateLeft8(n uint8, s int) uint8 {
    	// amd64:"ROLB" 386:"ROLB"
    	// arm64:"LSL","LSR",-"CSEL"
    	return bits.RotateLeft8(n, s)
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:51:17 UTC 2024
    - 19.6K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/riscv64.s

    	// 1.3: Bitwise Rotation (Zbb)
    	ROL	X8, X9, X10				// 33958460 or b30f8040b3dff4013395840033e5af00
    	ROL	X8, X9					// b3948460 or b30f8040b3dff401b3948400b3e49f00
    	ROLW	X9, X10, X11				// bb159560 or b30f9040bb5ff501bb159500b3e5bf00
    	ROLW	X9, X10					// 3b159560 or b30f9040bb5ff5013b15950033e5af00
    	ROR	X10, X11, X12				// 33d6a560 or b30fa040b39ff50133d6a50033e6cf00
    	ROR	X10, X11				// b3d5a560 or b30fa040b39ff501b3d5a500b3e5bf00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (RotateLeft16 <t> x y) => (OR (SLL  <t> x (ANDI [15] <y.Type> y)) (SRL <t> (ZeroExt16to64 x) (ANDI [15] <y.Type> (NEG <y.Type> y))))
    (RotateLeft32 ...) => (ROLW ...)
    (RotateLeft64 ...) => (ROL  ...)
    
    (Less64  ...) => (SLT  ...)
    (Less32  x y) => (SLT  (SignExt32to64 x) (SignExt32to64 y))
    (Less16  x y) => (SLT  (SignExt16to64 x) (SignExt16to64 y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"},      // arg0 | auxint
    		{name: "ROL", argLength: 2, reg: gp21, asm: "ROL"},                    // rotate left arg0 by (arg1 & 63)
    		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                  // rotate left least significant word of arg0 by (arg1 & 31), sign extended
    		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                    // rotate right arg0 by (arg1 & 63)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/x86/anames.go

    	"RDRANDQ",
    	"RDRANDW",
    	"RDSEEDL",
    	"RDSEEDQ",
    	"RDSEEDW",
    	"RDTSC",
    	"RDTSCP",
    	"REP",
    	"REPN",
    	"RETFL",
    	"RETFQ",
    	"RETFW",
    	"ROLB",
    	"ROLL",
    	"ROLQ",
    	"ROLW",
    	"RORB",
    	"RORL",
    	"RORQ",
    	"RORW",
    	"RORXL",
    	"RORXQ",
    	"ROUNDPD",
    	"ROUNDPS",
    	"ROUNDSD",
    	"ROUNDSS",
    	"RSM",
    	"RSQRTPS",
    	"RSQRTSS",
    	"SAHF",
    	"SALB",
    	"SALL",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/386Ops.go

    		{name: "ROLL", argLength: 2, reg: gp21shift, asm: "ROLL", resultInArg0: true, clobberFlags: true},               //     32 bits of arg0 rotate left by arg1
    		{name: "ROLW", argLength: 2, reg: gp21shift, asm: "ROLW", resultInArg0: true, clobberFlags: true},               // low 16 bits of arg0 rotate left by arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 14 08:10:32 UTC 2023
    - 45.1K bytes
    - Viewed (0)
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