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Results 1 - 8 of 8 for RORQ (0.06 sec)
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src/crypto/sha512/sha512block_amd64.s
#define MSGSCHEDULE1(index) \ MOVQ ((index-2)*8)(BP), AX; \ MOVQ AX, CX; \ RORQ $19, AX; \ MOVQ CX, DX; \ RORQ $61, CX; \ SHRQ $6, DX; \ MOVQ ((index-15)*8)(BP), BX; \ XORQ CX, AX; \ MOVQ BX, CX; \ XORQ DX, AX; \ RORQ $1, BX; \ MOVQ CX, DX; \ SHRQ $7, DX; \ RORQ $8, CX; \ ADDQ ((index-7)*8)(BP), AX; \ XORQ CX, BX; \ XORQ DX, BX; \ ADDQ ((index-16)*8)(BP), BX; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 27K bytes - Viewed (0) -
test/codegen/rotate.go
z &= 63 // amd64:"ROLQ",-"AND" // arm64:"ROR","NEG",-"AND" // ppc64x:"ROTL",-"NEG",-"AND" // loong64: "ROTRV", -"AND" // riscv64: "ROL",-"AND" a += x<<z | x>>(64-z) // amd64:"RORQ",-"AND" // arm64:"ROR",-"NEG",-"AND" // ppc64x:"ROTL","NEG",-"AND" // loong64: "ROTRV", -"AND" // riscv64: "ROR",-"AND" a += x>>z | x<<(64-z) return a }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 6K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
RORL $7, R11 // 41c1cb07 RORQ $1, (BX) // 48d10b RORQ $1, (R11) // 49d10b RORQ $1, DX // 48d1ca RORQ $1, R11 // 49d1cb RORQ CL, (BX) // 48d30b RORQ CL, (R11) // 49d30b RORQ CL, DX // 48d3ca
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// rotate left negative = rotate right (ROLQ x (NEG(Q|L) y)) => (RORQ x y) (ROLL x (NEG(Q|L) y)) => (RORL x y) (ROLW x (NEG(Q|L) y)) => (RORW x y) (ROLB x (NEG(Q|L) y)) => (RORB x y) // rotate right negative = rotate left (RORQ x (NEG(Q|L) y)) => (ROLQ x y) (RORL x (NEG(Q|L) y)) => (ROLL x y) (RORW x (NEG(Q|L) y)) => (ROLW x y) (RORB x (NEG(Q|L) y)) => (ROLB x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "ROLW", argLength: 2, reg: gp21shift, asm: "ROLW", resultInArg0: true, clobberFlags: true}, {name: "ROLB", argLength: 2, reg: gp21shift, asm: "ROLB", resultInArg0: true, clobberFlags: true}, {name: "RORQ", argLength: 2, reg: gp21shift, asm: "RORQ", resultInArg0: true, clobberFlags: true}, {name: "RORL", argLength: 2, reg: gp21shift, asm: "RORL", resultInArg0: true, clobberFlags: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v_1 := v.Args[1] v_0 := v.Args[0] // match: (ROLQ x (NEGQ y)) // result: (RORQ x y) for { x := v_0 if v_1.Op != OpAMD64NEGQ { break } y := v_1.Args[0] v.reset(OpAMD64RORQ) v.AddArg2(x, y) return true } // match: (ROLQ x (NEGL y)) // result: (RORQ x y) for { x := v_0 if v_1.Op != OpAMD64NEGL { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "RORQ", argLen: 2, resultInArg0: true, clobberFlags: true, asm: x86.ARORQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)