var a uint64

	z &= 63

	// amd64:"ROLQ",-"AND"
	// arm64:"ROR","NEG",-"AND"
	// ppc64x:"ROTL",-"NEG",-"AND"
	// loong64: "ROTRV", -"AND"
	// riscv64: "ROL",-"AND"
	a += x<<z | x>>(64-z)

	// amd64:"RORQ",-"AND"
	// arm64:"ROR",-"NEG",-"AND"
	// ppc64x:"ROTL","NEG",-"AND"
	// loong64: "ROTRV", -"AND"
	// riscv64: "ROR",-"AND"
	a += x>>z | x<<(64-z)

	return a
}

	MOV	(((index-2)&0xf)*8)(X19), X5; \
	MOV	(((index-15)&0xf)*8)(X19), X6; \
	MOV	(((index-7)&0xf)*8)(X19), X9; \
	MOV	(((index-16)&0xf)*8)(X19), X21; \
	ROR	$19, X5, X7; \
	ROR	$61, X5, X8; \
	SRL	$6, X5; \
	XOR	X7, X5; \
	XOR	X8, X5; \
	ADD	X9, X5; \
	ROR	$1, X6, X7; \
	ROR	$8, X6, X8; \
	SRL	$7, X6; \
	XOR	X7, X6; \
	XOR	X8, X6; \
	ADD	X6, X5; \
	ADD	X21, X5; \
	MOV	X5, ((index&0xf)*8)(X19)

	"ORN",
	"XNOR",
	"CLZ",
	"CLZW",
	"CTZ",
	"CTZW",
	"CPOP",
	"CPOPW",
	"MAX",
	"MAXU",
	"MIN",
	"MINU",
	"SEXTB",
	"SEXTH",
	"ZEXTH",
	"ROL",
	"ROLW",
	"ROR",
	"RORI",
	"RORIW",
	"RORW",
	"ORCB",
	"REV8",
	"BCLR",
	"BCLRI",
	"BEXT",
	"BEXTI",
	"BINV",
	"BINVI",
	"BSET",
	"BSETI",
	"WORD",
	"BEQZ",
	"BGEZ",
	"BGT",

	// arm64:"MOVD\t[$]-6148914691236517205","MOVD\t[$]3074457345618258602","MUL","ROR",-"DIV"
	// arm:"MUL","CMP\t[$]715827882",-".*udiv"
	// ppc64x:"MULLD","ROTL\t[$]63"
	even := n%6 == 0

	// amd64:"MOVQ\t[$]-8737931403336103397","IMULQ",-"ROLQ",-"DIVQ"
	// 386:"IMUL3L\t[$]678152731",-"ROLL",-"DIVQ"
	// arm64:"MOVD\t[$]-8737931403336103397","MUL",-"ROR",-"DIV"
	// arm:"MUL","CMP\t[$]226050910",-".*udiv"
	// ppc64x:"MULLD",-"ROTL"

		{name: "ROR", argLength: 2, reg: gp21, asm: "ROR"},                        // arg0 right rotate by (arg1 mod 64) bits
		{name: "RORW", argLength: 2, reg: gp21, asm: "RORW"},                      // arg0 right rotate by (arg1 mod 32) bits
		{name: "RORconst", argLength: 1, reg: gp11, asm: "ROR", aux: "Int64"},     // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63.

	"NGCW",
	"NOOP",
	"ORN",
	"ORNW",
	"ORR",
	"ORRW",
	"PRFM",
	"PRFUM",
	"RBIT",
	"RBITW",
	"REM",
	"REMW",
	"REV",
	"REV16",
	"REV16W",
	"REV32",
	"REVW",
	"ROR",
	"RORW",
	"SBC",
	"SBCS",
	"SBCSW",
	"SBCW",
	"SBFIZ",
	"SBFIZW",
	"SBFM",
	"SBFMW",
	"SBFX",
	"SBFXW",
	"SCVTFD",
	"SCVTFS",
	"SCVTFWD",
	"SCVTFWS",
	"SDIV",

	ROR:               "ROR",
	ROR_ZZ:            "ROR.ZZ",
	ROR_S_EQ:          "ROR.S.EQ",
	ROR_S_NE:          "ROR.S.NE",
	ROR_S_CS:          "ROR.S.CS",
	ROR_S_CC:          "ROR.S.CC",
	ROR_S_MI:          "ROR.S.MI",
	ROR_S_PL:          "ROR.S.PL",
	ROR_S_VS:          "ROR.S.VS",
	ROR_S_VC:          "ROR.S.VC",
	ROR_S_HI:          "ROR.S.HI",
	ROR_S_LS:          "ROR.S.LS",

	ROLW	X9, X10, X11				// bb159560 or b30f9040bb5ff501bb159500b3e5bf00
	ROLW	X9, X10					// 3b159560 or b30f9040bb5ff5013b15950033e5af00
	ROR	X10, X11, X12				// 33d6a560 or b30fa040b39ff50133d6a50033e6cf00
	ROR	X10, X11				// b3d5a560 or b30fa040b39ff501b3d5a500b3e5bf00
	ROR	$63, X11				// 93d5f563 or 93dff50393951500b3e5bf00
	RORI	$63, X11, X12				// 13d6f563 or 93dff5031396150033e6cf00

		if (x>>21)&1 != 0 {
			mode = AddrLDM_WB
		}
		return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode}

	case arg_R_rotate:
		Rm := Reg(x & (1<<4 - 1))
		typ, count := decodeShift(x)
		// ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1.
		if typ == RotateRightExt {
			return Rm
		}
		return RegShift{Rm, typ, count}

	case arg_R_shift_R:
		Rm := Reg(x & (1<<4 - 1))

	}
	return strings.ToUpper(arg.String())
}

// convert memory operand from GNU syntax to Plan 9 syntax, for example,
// [r5] -> (R5)
// [r6, #4080] -> 0xff0(R6)
// [r2, r0, ror #1] -> (R2)(R0@>1)
// inst [r2, -r0, ror #1] -> INST.U (R2)(R0@>1)
// input:
//
//	a memory operand
//
// return values:
//
//	corresponding memory operand in Plan 9 syntax
//	.W/.P/.U suffix