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Results 1 - 3 of 3 for ZEXTH (0.09 sec)
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src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
ORN X6, X7, X8 // 33e46340 ORN X6, X7 // b3e36340 SEXTB X16, X17 // 93184860 SEXTH X17, X18 // 13995860 XNOR X18, X19, X20 // 33ca2941 XNOR X18, X19 // b3c92941 ZEXTH X19, X20 // 3bca0908 // 1.3: Bitwise Rotation (Zbb) ROL X8, X9, X10 // 33958460 or b30f8040b3dff4013395840033e5af00 ROL X8, X9 // b3948460 or b30f8040b3dff401b3948400b3e49f00
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
ins.imm = 48 } ins2 := &instruction{as: ASRAI, rd: ins.rd, rs1: ins.rd, imm: ins.imm} inss = append(inss, ins2) } case AMOVHU, AMOVWU: if buildcfg.GORISCV64 >= 22 { // Use ZEXTH or ADDUW to extend. ins.as, ins.rs1, ins.rs2, ins.imm = AZEXTH, uint32(p.From.Reg), obj.REG_NONE, 0 if p.As == AMOVWU { ins.as, ins.rs2 = AADDUW, REG_ZERO } } else {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0)