// amd64:"ROLL\t[$]7"
	// arm:"MOVW\tR\\d+@>25"
	// ppc64x:"ROTLW\t[$]7"
	// loong64: "ROTR\t[$]25"
	// riscv64: "RORIW\t[$]25"
	a += x<<7 | x>>25

	// amd64:`ROLL\t[$]8`
	// arm:"MOVW\tR\\d+@>24"
	// arm64:"RORW\t[$]24"
	// s390x:"RLL\t[$]8"
	// ppc64x:"ROTLW\t[$]8"
	// loong64: "ROTR\t[$]24"
	// riscv64: "RORIW\t[$]24"
	a += x<<8 + x>>24

	// amd64:"ROLL\t[$]9"
	// arm:"MOVW\tR\\d+@>23"
	// arm64:"RORW\t[$]23"

	SRAI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
	RORIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	SLLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	SRLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	SRAIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
	RORIW	$-1, X5, X6			// ERROR "immediate out of range 0 to 31"

	"CLZ",
	"CLZW",
	"CTZ",
	"CTZW",
	"CPOP",
	"CPOPW",
	"MAX",
	"MAXU",
	"MIN",
	"MINU",
	"SEXTB",
	"SEXTH",
	"ZEXTH",
	"ROL",
	"ROLW",
	"ROR",
	"RORI",
	"RORIW",
	"RORW",
	"ORCB",
	"REV8",
	"BCLR",
	"BCLRI",
	"BEXT",
	"BEXTI",
	"BINV",
	"BINVI",
	"BSET",
	"BSETI",
	"WORD",
	"BEQZ",
	"BGEZ",
	"BGT",
	"BGTU",
	"BGTZ",

	ROR	$63, X11				// 93d5f563 or 93dff50393951500b3e5bf00
	RORI	$63, X11, X12				// 13d6f563 or 93dff5031396150033e6cf00
	RORI	$1, X12, X13				// 93561660 or 935f16009316f603b3e6df00
	RORIW	$31, X13, X14				// 1bd7f661 or 9bdff6011b97160033e7ef00
	RORIW	$1, X14, X15				// 9b571760 or 9b5f17009b17f701b3e7ff00
	RORW	X15, X16, X17				// bb58f860 or b30ff040bb1ff801bb58f800b3e81f01
	RORW	X15, X16				// 3b58f860 or b30ff040bb1ff8013b58f80033e80f01

(XOR (MOVDconst [val]) x) && is32Bit(val) => (XORI [val] x)
(ROL  x (MOVDconst [val])) => (RORI  [int64(int8(-val)&63)] x)
(ROLW x (MOVDconst [val])) => (RORIW [int64(int8(-val)&31)] x)
(ROR  x (MOVDconst [val])) => (RORI  [int64(val&63)] x)
(RORW x (MOVDconst [val])) => (RORIW [int64(val&31)] x)
(SLL  x (MOVDconst [val])) => (SLLI [int64(val&63)] x)
(SRL  x (MOVDconst [val])) => (SRLI [int64(val&63)] x)

		{name: "RORI", argLength: 1, reg: gp11, asm: "RORI", aux: "Int64"},    // rotate right arg0 by auxint, shift amount 0-63
		{name: "RORIW", argLength: 1, reg: gp11, asm: "RORIW", aux: "Int64"},  // rotate right least significant word of arg0 by auxint, shift amount 0-31, sign extended

	// result: (MOVDreg x)
	for {
		x := v_0
		if x.Op != OpRISCV64RORW {
			break
		}
		v.reset(OpRISCV64MOVDreg)
		v.AddArg(x)
		return true
	}
	// match: (MOVWreg x:(RORIW _))
	// result: (MOVDreg x)
	for {
		x := v_0
		if x.Op != OpRISCV64RORIW {
			break
		}
		v.reset(OpRISCV64MOVDreg)
		v.AddArg(x)
		return true
	}

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "RORIW",
		auxType: auxInt64,
		argLen:  1,
		asm:     riscv.ARORIW,
		reg: regInfo{
			inputs: []inputInfo{