return fmt.Sprintf("W%d", int(r-W0))
	case X0 <= r && r <= X30:
		return fmt.Sprintf("X%d", int(r-X0))

	case B0 <= r && r <= B31:
		return fmt.Sprintf("B%d", int(r-B0))
	case H0 <= r && r <= H31:
		return fmt.Sprintf("H%d", int(r-H0))
	case S0 <= r && r <= S31:
		return fmt.Sprintf("S%d", int(r-S0))
	case D0 <= r && r <= D31:
		return fmt.Sprintf("D%d", int(r-D0))
	case Q0 <= r && r <= Q31:

		return &inst{0x2f, 0x2, 0x0, -512, 0x70}
	case AAMOMIND:
		return &inst{0x2f, 0x3, 0x0, -2048, 0x40}
	case AAMOMINW:
		return &inst{0x2f, 0x2, 0x0, -2048, 0x40}
	case AAMOMINUD:
		return &inst{0x2f, 0x3, 0x0, -1024, 0x60}
	case AAMOMINUW:
		return &inst{0x2f, 0x2, 0x0, -1024, 0x60}
	case AAMOORD:
		return &inst{0x2f, 0x3, 0x0, 1024, 0x20}
	case AAMOORW:
		return &inst{0x2f, 0x2, 0x0, 1024, 0x20}
	case AAMOSWAPD:

	if op >= Op(len(opstr)) || opstr[op] == "" {
		return fmt.Sprintf("Op(%d)", int(op))
	}
	return opstr[op]
}

// An Inst is a single instruction.
type Inst struct {
	Op   Op     // Opcode mnemonic
	Enc  uint32 // Raw encoding bits.
	Len  int    // Length of encoding in bytes.
	Args Args   // Instruction arguments, in ARM manual order.
}

func (i Inst) String() string {
	var buf bytes.Buffer
	buf.WriteString(i.Op.String())

import (
	"bytes"
	"fmt"
)

// An Inst is a single instruction.
type Inst struct {
	Prefix   Prefixes // Prefixes applied to the instruction.
	Op       Op       // Opcode mnemonic
	Opcode   uint32   // Encoded opcode bits, left aligned (first byte is Opcode>>24, etc)
	Args     Args     // Instruction arguments, in Intel order
	Mode     int      // processor mode in bits: 16, 32, or 64
	AddrSize int      // address size in bits: 16, 32, or 64

	case R0 <= r && r <= R31:
		return fmt.Sprintf("r%d", int(r-R0))
	case F0 <= r && r <= F31:
		return fmt.Sprintf("f%d", int(r-F0))
	case V0 <= r && r <= V31:
		return fmt.Sprintf("v%d", int(r-V0))
	case VS0 <= r && r <= VS63:
		return fmt.Sprintf("vs%d", int(r-VS0))
	case A0 <= r && r <= A7:
		return fmt.Sprintf("a%d", int(r-A0))
	default:
		return fmt.Sprintf("Reg(%d)", int(r))
	}
}

{"Name":"INS (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is used by the alias MOV (element)."},

		if inst.Op == NOP && inst.Opcode>>24 != 0x90 {
			break
		}
		if inst.Op == RET && inst.Opcode>>24 != 0xC3 {
			break
		}
		if inst.Op == INT && inst.Opcode>>24 != 0xCC {
			break
		}
		if inst.Op == LRET && inst.Opcode>>24 != 0xcb {
			break
		}
		for i, p := range inst.Prefix {
			if p&0xFF == PrefixDataSize {
				inst.Prefix[i] &^= PrefixImplicit | PrefixIgnored
			}
		}

		if isMem(inst.Args[0]) {
			unmarkImplicit(&inst, PrefixDataSize)
		}

	case SYSEXIT:
		unmarkImplicit(&inst, PrefixDataSize)
	}

	if isCondJmp[inst.Op] || isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ {
		if countPrefix(&inst, PrefixCS) > 0 && countPrefix(&inst, PrefixDS) > 0 {
			for i, p := range inst.Prefix {
				switch p & 0xFFF {

		if reg == R0 {
			return fmt.Sprintf("%d(0)", int(arg))
		}
		return fmt.Sprintf("%d(r%d)", int(arg), reg-R0)
	}
	return fmt.Sprintf("???(%v)", arg)
}

// removeArg removes the arg in inst.Args[index].
func removeArg(inst *Inst, index int) {
	for i := index; i < len(inst.Args); i++ {
		if i+1 < len(inst.Args) {
			inst.Args[i] = inst.Args[i+1]
		} else {
			inst.Args[i] = nil
		}
	}
}

func GNUSyntax(inst Inst) string {
	switch inst.Op {
	case RET:
		if r, ok := inst.Args[0].(Reg); ok && r == X30 {
			return "ret"
		}
	case B:
		if _, ok := inst.Args[0].(Cond); ok {
			return strings.ToLower("b." + inst.Args[0].String() + " " + inst.Args[1].String())
		}
	case SYSL:
		result := strings.ToLower(inst.String())
		return strings.Replace(result, "c", "C", -1)