LDP.P	32(R9), (R15, R16)
	LDP	-16(R9), (R17, R19)
	SBCS	R15, R11
	SBCS	R16, R12
	SBCS	R17, R13
	SBCS	R19, R14
	STP.P	(R11, R12), 32(R10)
	STP	(R13, R14), -16(R10)
	SUB	$4, R0
	B	loop
done:
	CSET	LO, R0		// extract carry flag
	MOVD	R0, c+72(FP)
	RET

#define vwOneOp(instr, op1)				\
	MOVD.P	8(R1), R4;				\
	instr	op1, R4;				\
	MOVD.P	R4, 8(R3);

	ADC	$0, hlp0, acc3

	ADDS	acc4, acc0, acc0
	ADCS	acc5, acc1, acc1
	ADCS	acc6, acc2, acc2
	ADCS	acc7, acc3, acc3
	ADC	$0, ZR, acc4

	SUBS	const0, acc0, y0
	SBCS	const1, acc1, y1
	SBCS	const2, acc2, y2
	SBCS	const3, acc3, y3
	SBCS	$0, acc4, acc4

	CSEL	CS, y0, acc0, x0
	CSEL	CS, y1, acc1, x1
	CSEL	CS, y2, acc2, x2
	CSEL	CS, y3, acc3, x3

	CBNZ	b_ptr, ordSqrLoop

	MOVD	res+0(FP), res_ptr

	// amd64:"NEGL","SBBQ","NEGQ"
	// arm64:"NEGS","SBCS","NGC","NEG",-"ADD",-"SUB",-"CMP"
	// loong64:"SUBV","SGTU"
	// ppc64x:"SUBC", "SUBE", "SUBZE", "NEG"
	// s390x:"SUBE"
	// mips64:"SUBV","SGTU"
	// riscv64: "SUB","SLTU"
	return bits.Sub(x, y, ci)
}

func SubC(x, ci uint) (r, co uint) {
	// amd64:"NEGL","SBBQ","NEGQ"
	// arm64:"NEGS","SBCS","NGC","NEG",-"ADD",-"SUB",-"CMP"
	// loong64:"SUBV","SGTU"

	"ORNW",
	"ORR",
	"ORRW",
	"PRFM",
	"PRFUM",
	"RBIT",
	"RBITW",
	"REM",
	"REMW",
	"REV",
	"REV16",
	"REV16W",
	"REV32",
	"REVW",
	"ROR",
	"RORW",
	"SBC",
	"SBCS",
	"SBCSW",
	"SBCW",
	"SBFIZ",
	"SBFIZW",
	"SBFM",
	"SBFMW",
	"SBFX",
	"SBFXW",
	"SCVTFD",
	"SCVTFS",
	"SCVTFWD",
	"SCVTFWS",
	"SDIV",
	"SDIVW",
	"SEV",
	"SEVL",

	// NGCS <Wd>, <Wm>
	{0xffe0ffe0, 0x7a0003e0, NGCS, instArgs{arg_Wd, arg_Wm}, nil},
	// SBCS <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x7a000000, SBCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
	// NGCS <Xd>, <Xm>
	{0xffe0ffe0, 0xfa0003e0, NGCS, instArgs{arg_Xd, arg_Xm}, nil},
	// SBCS <Xd>, <Xn>, <Xm>
	{0xffe0fc00, 0xfa000000, SBCS, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// PRFM <prfop>, [<Xn|SP>{, #<pimm>}]

	ROR R0, R23, R2                            // e22ec09a
	SBCW R4, R8, R24                           // 1801045a
	SBC R25, R10, R26                          // 5a0119da
	SBCSW R27, R19, R19                        // 73021b7a
	SBCS R5, R9, R5                            // 250105fa
	SBFIZW $9, R10, $18, R22                   // 56451713
	SBFIZ $6, R11, $15, R20                    // 74397a93
	SBFXW $8, R15, $10, R20                    // f4450813

{"Name":"SBCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBCS <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
{"Name":"SBCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBCS <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGCS."},

		{name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int64"},                                         // arg0 - auxInt
		{name: "SBCSflags", argLength: 3, reg: gp2flags1flags, typ: "(UInt64,Flags)", asm: "SBCS"},                    // arg0-(arg1+borrowing), set flags.
		{name: "SUBSflags", argLength: 2, reg: gp21flags, typ: "(UInt64,Flags)", asm: "SUBS"},                         // arg0 - arg1, set flags.

	// MADD Rn,Rm,Ra,Rd
	MADD	R1, R2, R3, R4                   // 6408019b
	// CLS
	CLSW	R1, R2
	CLS	R1, R2
	SBC	$0, R1                           // 21001fda
	SBCW	$0, R1                           // 21001f5a
	SBCS	$0, R1                           // 21001ffa
	SBCSW	$0, R1                           // 21001f7a
	ADC	$0, R1                           // 21001f9a
	ADCW	$0, R1                           // 21001f1a