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Results 1 - 10 of 28 for SRA (0.02 sec)
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src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/go/internal/gccgoimporter/ar.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Sep 30 14:14:36 UTC 2022 - 4.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
"FMULAF", "FMULAD", "FNMULAF", "FNMULAD", "FMULSF", "FMULSD", "FNMULSF", "FNMULSD", "DIVF", "DIVD", "SQRTF", "SQRTD", "ABSF", "ABSD", "NEGF", "NEGD", "SRL", "SRA", "SLL", "MULU", "DIVU", "MUL", "MMUL", "DIV", "MOD", "MODU", "DIVHW", "DIVUHW", "MOVB", "MOVBS", "MOVBU", "MOVH", "MOVHS", "MOVHU", "MOVW", "MOVM",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
AND R4, R5 // a5901400 NEGW R4, R5 // 05101100 NEGV R4, R5 // 05901100 SLL R4, R5 // a5101700 SLL R4, R5, R6 // a6101700 SRL R4, R5 // a5901700 SRL R4, R5, R6 // a6901700 SRA R4, R5 // a5101800 SRA R4, R5, R6 // a6101800 ROTR R4, R5 // a5101b00 ROTR R4, R5, R6 // a6101b00 SLLV R4, R5 // a5901800 SLLV R4, R5, R6 // a6901800 ROTRV R4, R5 // a5901b00 ROTRV R4, R5, R6 // a6901b00
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(RSB (SRL y z) x) => (SUBshiftRLreg x y z) (RSB x (SRA y z)) => (RSBshiftRAreg x y z) (RSB (SRA y z) x) => (SUBshiftRAreg x y z) (AND x (SLLconst [c] y)) => (ANDshiftLL x y [c]) (AND x (SRLconst [c] y)) => (ANDshiftRL x y [c]) (AND x (SRAconst [c] y)) => (ANDshiftRA x y [c]) (AND x (SLL y z)) => (ANDshiftLLreg x y z) (AND x (SRL y z)) => (ANDshiftRLreg x y z) (AND x (SRA y z)) => (ANDshiftRAreg x y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
SRA.S $31, R5, R6 // c56fb0e1 SRA $14, R5 // 4557a0e1 SRA $15, R5 // c557a0e1 SRA $30, R5 // 455fa0e1 SRA $31, R5 // c55fa0e1 SRA.S $14, R5 // 4557b0e1 SRA.S $15, R5 // c557b0e1 SRA.S $30, R5 // 455fb0e1 SRA.S $31, R5 // c55fb0e1 SRA R5, R6, R7 // 5675a0e1 SRA.S R5, R6, R7 // 5675b0e1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
test/codegen/shift.go
// s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func rshMask64x64(v int64, s uint64) int64 { // arm64:"ASR",-"AND",-"CSEL" // ppc64x:"RLDICL",-"ORN",-"ISEL" // riscv64:"SRA\t",-"OR",-"SLTIU" // s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func lshMask32x64(v int32, s uint64) int32 { // arm64:"LSL",-"AND" // ppc64x:"ISEL",-"ORN" // riscv64:"SLL",-"AND\t",-"SLTIU"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0)