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Results 1 - 10 of 16 for ROTR (0.03 sec)
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src/cmd/internal/notsha256/sha256block_386.s
#define MSGSCHEDULE0(index) \ MOVL (index*4)(SI), AX; \ BSWAPL AX; \ MOVL AX, (index*4)(BP) // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVL ((index-2)*4)(BP), AX; \ MOVL AX, CX; \ RORL $17, AX; \ MOVL CX, DX; \ RORL $19, CX; \ SHRL $10, DX; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 8.2K bytes - Viewed (0) -
src/crypto/sha512/sha512block_riscv64.s
OR X5, X6, X5; \ SLL $8, X7; \ OR X5, X7, X5; \ OR X5, X8, X5; \ MOV X5, (index*8)(X19) // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 79 // SIGMA0(x) = ROTR(1,x) XOR ROTR(8,x) XOR SHR(7,x) // SIGMA1(x) = ROTR(19,x) XOR ROTR(61,x) XOR SHR(6,x) #define MSGSCHEDULE1(index) \ MOV (((index-2)&0xf)*8)(X19), X5; \ MOV (((index-15)&0xf)*8)(X19), X6; \ MOV (((index-7)&0xf)*8)(X19), X9; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 9.1K bytes - Viewed (0) -
test/codegen/rotate.go
var a uint32 // amd64:"ROLL\t[$]7" // arm:"MOVW\tR\\d+@>25" // ppc64x:"ROTLW\t[$]7" // loong64: "ROTR\t[$]25" // riscv64: "RORIW\t[$]25" a += x<<7 | x>>25 // amd64:`ROLL\t[$]8` // arm:"MOVW\tR\\d+@>24" // arm64:"RORW\t[$]24" // s390x:"RLL\t[$]8" // ppc64x:"ROTLW\t[$]8" // loong64: "ROTR\t[$]24" // riscv64: "RORIW\t[$]24" a += x<<8 + x>>24 // amd64:"ROLL\t[$]9" // arm:"MOVW\tR\\d+@>23"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 6K bytes - Viewed (0) -
src/crypto/sha256/sha256block_386.s
#define MSGSCHEDULE0(index) \ MOVL (index*4)(SI), AX; \ BSWAPL AX; \ MOVL AX, (index*4)(BP) // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVL ((index-2)*4)(BP), AX; \ MOVL AX, CX; \ RORL $17, AX; \ MOVL CX, DX; \ RORL $19, CX; \ SHRL $10, DX; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
NEGV R4, R5 // 05901100 SLL R4, R5 // a5101700 SLL R4, R5, R6 // a6101700 SRL R4, R5 // a5901700 SRL R4, R5, R6 // a6901700 SRA R4, R5 // a5101800 SRA R4, R5, R6 // a6101800 ROTR R4, R5 // a5101b00 ROTR R4, R5, R6 // a6101b00 SLLV R4, R5 // a5901800 SLLV R4, R5, R6 // a6901800 ROTRV R4, R5 // a5901b00 ROTRV R4, R5, R6 // a6901b00 CLO R4, R5 // 85100000 CLZ R4, R5 // 85140000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/internal/notsha256/sha256block_amd64.s
#define MSGSCHEDULE0(index) \ MOVL (index*4)(SI), AX; \ BSWAPL AX; \ MOVL AX, (index*4)(BP) // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63 // SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x) // SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x) #define MSGSCHEDULE1(index) \ MOVL ((index-2)*4)(BP), AX; \ MOVL AX, CX; \ RORL $17, AX; \ MOVL CX, DX; \ RORL $19, CX; \ SHRL $10, DX; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14K bytes - Viewed (0) -
.idea/dictionaries/svyatoslav_kuzmich.xml
Registered: Wed Jun 12 09:53:16 UTC 2024 - Last Modified: Tue Oct 12 05:42:01 UTC 2021 - 594 bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
"MOVWF", "MOVWL", "MOVWR", "MSUB", "MUL", "MULD", "MULF", "MULU", "MULW", "NEGD", "NEGF", "NEGW", "NEGV", "NOOP", "NOR", "OR", "REM", "REMU", "RFE", "ROTR", "ROTRV", "SC", "SCV", "SEB", "SEH", "SGT", "SGTU", "SLL", "SQRTD", "SQRTF", "SRA", "SRL", "SUB", "SUBD", "SUBF", "SUBU", "SUBW", "SYNC", "SYSCALL",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
SRAV R20, R19, R19 // 02939817 ROTR R19, R18, R20 // 0272a046 ROTRV R9, R13, R16 // 012d8056 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL R1, R2 // 00221004 SLLV R10, R22 // 0156b014 SRL R27, R6 // 03663006 SRLV R27, R6 // 03663016 SRA R11, R19 // 01739807 SRAV R20, R19 // 02939817 ROTR R20, R19 // 02939846 ROTRV R16, R9 // 02094856
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0)