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Results 1 - 10 of 19 for SLLV (0.04 sec)

  1. src/internal/runtime/atomic/atomic_loong64.s

    	MOVBU	val+8(FP), R5
    	// Align ptr down to 4 bytes so we can use 32-bit load/store.
    	MOVV	$~3, R6
    	AND	R4, R6
    	// R7 = ((ptr & 3) * 8)
    	AND	$3, R4, R7
    	SLLV	$3, R7
    	// Shift val for aligned ptr. R5 = val << R7 | ^(0xFF << R7)
    	MOVV	$0xFF, R8
    	SLLV	R7, R5
    	SLLV	R7, R8
    	NOR	R0, R8
    	OR	R8, R5
    
    	DBAR
    	LL	(R6), R7
    	AND	R5, R7
    	SC	R7, (R6)
    	BEQ	R7, -4(PC)
    	DBAR
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 6.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
    (Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
    (Lsh64x8  <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64  y))) (SLLV <t> x (ZeroExt8to64  y)))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Lsh64x64 <t> x y) => (MASKEQZ (SLLV <t> x                y)  (SGTU (MOVVconst <typ.UInt64> [64])                y))
    (Lsh64x32 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
    (Lsh64x16 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    	SLLV	R4, R5			// a5901800
    	SLLV	R4, R5, R6		// a6901800
    	ROTRV	R4, R5			// a5901b00
    	ROTRV	R4, R5, R6		// a6901b00
    	CLO	R4, R5			// 85100000
    	CLZ	R4, R5			// 85140000
    	ADDF	F4, F5			// a5900001
    	ADDF	F4, R5, F6		// a6900001
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  5. src/runtime/rt0_openbsd_mips64.s

    TEXT main(SB),NOSPLIT|NOFRAME,$0
    	// in external linking, glibc jumps to main with argc in R4
    	// and argv in R5
    
    	// initialize REGSB = PC&0xffffffff00000000
    	BGEZAL	R0, 1(PC)
    	SRLV	$32, R31, RSB
    	SLLV	$32, RSB
    
    	MOVV	$runtime·rt0_go(SB), R1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 29 08:07:46 UTC 2020
    - 976 bytes
    - Viewed (0)
  6. src/internal/runtime/atomic/atomic_mips64x.s

    	// Compute val shift.
    #ifdef GOARCH_mips64
    	// Big endian.  ptr = ptr ^ 3
    	XOR	$3, R1
    #endif
    	// R4 = ((ptr & 3) * 8)
    	AND	$3, R1, R4
    	SLLV	$3, R4
    	// Shift val for aligned ptr. R2 = val << R4 | ^(0xFF << R4)
    	MOVV	$0xFF, R5
    	SLLV	R4, R2
    	SLLV	R4, R5
    	NOR	R0, R5
    	OR	R5, R2
    
    	SYNC
    	LL	(R3), R4
    	AND	R2, R4
    	SC	R4, (R3)
    	BEQ	R4, -4(PC)
    	SYNC
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 21:29:34 UTC 2024
    - 7.2K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/mips/anames.go

    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"SYNC",
    	"SYSCALL",
    	"TEQ",
    	"TLBP",
    	"TLBR",
    	"TLBWI",
    	"TLBWR",
    	"TNE",
    	"WORD",
    	"WSBH",
    	"XOR",
    	"MOVV",
    	"MOVVL",
    	"MOVVR",
    	"SLLV",
    	"SRAV",
    	"SRLV",
    	"DIVV",
    	"DIVVU",
    	"REMV",
    	"REMVU",
    	"MULV",
    	"MULVU",
    	"ADDV",
    	"ADDVU",
    	"SUBV",
    	"SUBVU",
    	"DSBH",
    	"DSHD",
    	"TRUNCFV",
    	"TRUNCDV",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  8. src/runtime/rt0_linux_mips64x.s

    TEXT main(SB),NOSPLIT|NOFRAME,$0
    	// in external linking, glibc jumps to main with argc in R4
    	// and argv in R5
    
    	// initialize REGSB = PC&0xffffffff00000000
    	BGEZAL	R0, 1(PC)
    	SRLV	$32, R31, RSB
    	SLLV	$32, RSB
    
    	MOVV	$runtime·rt0_go(SB), R1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat Nov 06 10:24:44 UTC 2021
    - 1014 bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/mips64.s

    //	}
    	SLL	R1, R2, R3	// 00221804
    	SLLV	R10, R22, R21	// 0156a814
    	SRL	R27, R6, R17	// 03668806
    	SRLV	R27, R6, R17	// 03668816
    	SRA	R11, R19, R20	// 0173a007
    	SRAV	R20, R19, R19	// 02939817
    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/loong64/anames.go

    	"ROTR",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    	"MOVV",
    	"MOVVL",
    	"MOVVR",
    	"SLLV",
    	"SRAV",
    	"SRLV",
    	"ROTRV",
    	"DIVV",
    	"DIVVU",
    	"REMV",
    	"REMVU",
    	"MULV",
    	"MULVU",
    	"MULHV",
    	"MULHVU",
    	"ADDV",
    	"ADDVU",
    	"SUBV",
    	"SUBVU",
    	"TRUNCFV",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
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