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Results 1 - 10 of 14 for DIVVU (0.07 sec)

  1. src/cmd/internal/obj/mips/anames.go

    	"SYSCALL",
    	"TEQ",
    	"TLBP",
    	"TLBR",
    	"TLBWI",
    	"TLBWR",
    	"TNE",
    	"WORD",
    	"WSBH",
    	"XOR",
    	"MOVV",
    	"MOVVL",
    	"MOVVR",
    	"SLLV",
    	"SRAV",
    	"SRLV",
    	"DIVV",
    	"DIVVU",
    	"REMV",
    	"REMVU",
    	"MULV",
    	"MULVU",
    	"ADDV",
    	"ADDVU",
    	"SUBV",
    	"SUBVU",
    	"DSBH",
    	"DSHD",
    	"TRUNCFV",
    	"TRUNCDV",
    	"TRUNCFW",
    	"TRUNCDW",
    	"MOVWU",
    	"MOVFV",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
    (Div(32|64)F ...) => (DIV(F|D) ...)
    
    (Mod64 x y) => (Select0 (DIVV x y))
    (Mod64u x y) => (Select0 (DIVVU x y))
    (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
    (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
    (Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
    (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/loong64/anames.go

    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    	"MOVV",
    	"MOVVL",
    	"MOVVR",
    	"SLLV",
    	"SRAV",
    	"SRLV",
    	"ROTRV",
    	"DIVV",
    	"DIVVU",
    	"REMV",
    	"REMVU",
    	"MULV",
    	"MULVU",
    	"MULHV",
    	"MULHVU",
    	"ADDV",
    	"ADDVU",
    	"SUBV",
    	"SUBVU",
    	"TRUNCFV",
    	"TRUNCDV",
    	"TRUNCFW",
    	"TRUNCDW",
    	"MOVWU",
    	"MOVFV",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	REMV	R4, R5	   		// a5902200
    	REMV	R4, R5, R6	   	// a6902200
    	REMVU	R4, R5			// a5902300
    	REMVU	R4, R5, R6		// a6902300
    	DIVV	R4, R5			// a5102200
    	DIVV	R4, R5, R6	   	// a6102200
    	DIVVU	R4, R5	 		// a5102300
    	DIVVU	R4, R5, R6		// a6102300
    
    	MOVH	R4, result+16(FP)	// 64604029
    	MOVH	R4, 1(R5)		// a4044029
    	MOVH	y+8(FP), R4		// 64404028
    	MOVH	1(R5), R4		// a4044028
    	MOVHU	R4, R5			// 8500cf00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Div64 x y) => (DIVV x y)
    (Div64u ...) => (DIVVU ...)
    (Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y))
    (Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))
    (Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y))
    (Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))
    (Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y))
    (Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))
    (Div(32|64)F ...) => (DIV(F|D) ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "DIVV", argLength: 2, reg: gp21, asm: "DIVV", typ: "Int64"},                         // arg0 / arg1, signed
    		{name: "DIVVU", argLength: 2, reg: gp21, asm: "DIVVU", typ: "UInt64"},                      // arg0 / arg1, unsigned
    		{name: "REMV", argLength: 2, reg: gp21, asm: "REMV", typ: "Int64"},                         // arg0 / arg1, signed
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "DIVV", argLength: 2, reg: gp2hilo, asm: "DIVV", typ: "(Int64,Int64)"},                        // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1
    		{name: "DIVVU", argLength: 2, reg: gp2hilo, asm: "DIVVU", typ: "(UInt64,UInt64)"},                    // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1
    
    		{name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  8. src/runtime/sys_linux_mips64x.s

    	SYSCALL
    	BEQ	R7, 2(PC)
    	SUBVU	R2, R0, R2	// caller expects negative errno
    	MOVW	R2, errno+16(FP)
    	RET
    
    TEXT runtimeĀ·usleep(SB),NOSPLIT,$16-4
    	MOVWU	usec+0(FP), R3
    	MOVV	R3, R5
    	MOVW	$1000000, R4
    	DIVVU	R4, R3
    	MOVV	LO, R3
    	MOVV	R3, 8(R29)
    	MOVW	$1000, R4
    	MULVU	R3, R4
    	MOVV	LO, R4
    	SUBVU	R4, R5
    	MOVV	R5, 16(R29)
    
    	// nanosleep(&ts, 0)
    	ADDV	$8, R29, R4
    	MOVW	$0, R5
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Oct 18 20:57:24 UTC 2022
    - 12K bytes
    - Viewed (0)
  9. src/runtime/sys_openbsd_mips64.s

    	SYSCALL
    	BEQ	R7, 2(PC)
    	SUBVU	R2, R0, R2	// caller expects negative errno
    	MOVW	R2, ret+24(FP)
    	RET
    
    TEXT runtimeĀ·usleep(SB),NOSPLIT,$24-4
    	MOVWU	usec+0(FP), R3
    	MOVV	R3, R5
    	MOVW	$1000000, R4
    	DIVVU	R4, R3
    	MOVV	LO, R3
    	MOVV	R3, 8(R29)		// tv_sec
    	MOVW	$1000, R4
    	MULVU	R3, R4
    	MOVV	LO, R4
    	SUBVU	R4, R5
    	MOVV	R5, 16(R29)		// tv_nsec
    
    	ADDV	$8, R29, R4		// arg 1 - rqtp
    	MOVV	$0, R5			// arg 2 - rmtp
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Jun 06 18:49:01 UTC 2023
    - 8.8K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/mips64.s

    	MULVU	R21, R13	// 01b5001d
    
    //	LDIV rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	DIV	R18, R22	// 02d2001a
    	DIVU	R14, R9		// 012e001b
    	DIVV	R8, R13		// 01a8001e
    	DIVVU	R16, R19	// 0270001f
    
    //	LREM rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	REM	R18, R22	// 02d2001a
    	REMU	R14, R9		// 012e001b
    	REMV	R8, R13		// 01a8001e
    	REMVU	R16, R19	// 0270001f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
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