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src/internal/runtime/atomic/atomic_loong64.s

	MOVV	ptr+0(FP), R4
	MOVV	val+8(FP), R5
	DBAR
	LLV	(R4), R6
	OR	R5, R6, R7
	SCV	R7, (R4)
	BEQ	R7, -4(PC)
	DBAR
	MOVV R6, ret+16(FP)
	RET

// func And64(addr *uint64, v uint64) old uint64
TEXT ·And64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R4
	MOVV	val+8(FP), R5
	DBAR
	LLV	(R4), R6
	AND	R5, R6, R7
	SCV	R7, (R4)
	BEQ	R7, -4(PC)
	DBAR
	MOVV R6, ret+16(FP)
	RET

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Mon Mar 25 19:53:03 UTC 2024

- 6.3K bytes

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github.com/golang/go

src/internal/cpu/cpu_ppc64x.go

//go:build ppc64 || ppc64le

package cpu

const CacheLinePadSize = 128

func doinit() {
	options = []option{
		{Name: "darn", Feature: &PPC64.HasDARN},
		{Name: "scv", Feature: &PPC64.HasSCV},
		{Name: "power9", Feature: &PPC64.IsPOWER9},
	}

	osinit()
}

func isSet(hwc uint, value uint) bool {
	return hwc&value != 0
}

func Name() string {
	switch {

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue May 10 20:05:43 UTC 2022

- 651 bytes

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github.com/golang/go

src/internal/runtime/atomic/atomic_mips64x.s

	MOVV	val+8(FP), R2

	SYNC
	LLV	(R1), R3
	OR	R2, R3, R4
	SCV	R4, (R1)
	BEQ	R4, -3(PC)
	SYNC
	MOVV	R3, ret+16(FP)
	RET

// func And64(addr *uint64, v uint64) old uint64
TEXT ·And64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R1
	MOVV	val+8(FP), R2

	SYNC
	LLV	(R1), R3
	AND	R2, R3, R4
	SCV	R4, (R1)
	BEQ	R4, -3(PC)
	SYNC
	MOVV	R3, ret+16(FP)
	RET

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Sat May 11 21:29:34 UTC 2024

- 7.2K bytes

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github.com/golang/go

src/vendor/golang.org/x/sys/cpu/cpu_ppc64x.go

//go:build ppc64 || ppc64le

package cpu

const cacheLineSize = 128

func initOptions() {
	options = []option{
		{Name: "darn", Feature: &PPC64.HasDARN},
		{Name: "scv", Feature: &PPC64.HasSCV},
	}

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Oct 19 23:33:33 UTC 2023

- 360 bytes

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github.com/golang/go

src/cmd/internal/obj/mips/anames.go

	"MSUB",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"ROTR",
	"ROTRV",
	"SC",
	"SCV",
	"SEB",
	"SEH",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",
	"SYNC",
	"SYSCALL",
	"TEQ",
	"TLBP",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue Aug 08 12:17:12 UTC 2023

- 1.4K bytes

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github.com/golang/go

src/cmd/internal/obj/loong64/anames.go

	"MOVWR",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULH",
	"MULHU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"SC",
	"SCV",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"ROTR",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",
	"DBAR",
	"SYSCALL",
	"TEQ",
	"TNE",
	"WORD",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 02:04:54 UTC 2024

- 1.9K bytes

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github.com/golang/go

src/internal/cpu/cpu.go

	_      CacheLinePad
}

// For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00,
// since there are no optional categories. There are some exceptions that also
// require kernel support to work (darn, scv), so there are feature bits for
// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
// The struct is padded to avoid false sharing.
var PPC64 struct {
	_         CacheLinePad

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 15 19:57:43 UTC 2024

- 7.1K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/loong64enc1.s

	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029
	MOVB	R4, 1(R5)		// a4040029
	MOVBU	R4, 1(R5)		// a4040029
	MOVWL	R4, 1(R5)		// a404002f
	MOVVL	R4, 1(R5)		// a404802f
	SC	R4, 1(R5)		// a4040021
	SCV	R4, 1(R5)		// a4040023
	MOVW	y+8(FP), R4		// 64408028
	MOVWU	y+8(FP), R4		// 6440802a
	MOVV	y+8(FP), R4		// 6440c028
	MOVB	y+8(FP), R4		// 64400028
	MOVBU	y+8(FP), R4		// 6440002a
	MOVWL	y+8(FP), R4		// 6440002e

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 02:04:54 UTC 2024

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github.com/golang/go

src/vendor/golang.org/x/sys/cpu/cpu.go

//
// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
// since there are no optional categories. There are some exceptions that also
// require kernel support to work (DARN, SCV), so there are feature bits for
// those as well. The struct is padded to avoid false sharing.
var PPC64 struct {
	_        CacheLinePad
	HasDARN  bool // Hardware random number generator (requires kernel enablement)

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 08 16:12:58 UTC 2024

- 12.1K bytes

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/mips64.s

//
//	LMOVV rreg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVV	R1, foo<>+3(SB)
	MOVV	R18, (R5)	// fcb20000
	MOVV	R4, 8(R16)	// fe040008
	MOVV	R1, -32(R14)	// fdc1ffe0
	SCV	R1, (R2)	// f0410000

//	LMOVW rreg ',' addr
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVW	R1, foo<>+3(SB)
	MOVW	R8, (R3)	// ac680000
	MOVW	R11, 19(R2)	// ac4b0013
	MOVW	R25, -89(R22)	// aed9ffa7

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue Aug 08 12:17:12 UTC 2023

- 12.4K bytes

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