//	LFADD freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	ADDD	F1, F2

//	LFADD freg ',' freg ',' freg
//	{
//		outcode(int($1), &$2, int($4.Reg), &$6);
//	}
	ADDD	F1, F2, F3

//	LFCMP freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	CMPEQD	F1, F2


//
// WORD
//
	WORD	$1	// 00000001
	NOOP		// 00000000
	SYNC		// 0000000f

//

	//	}
	ADD	$4, R1

	//	LMUL rreg ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	MUL	R1, R2

	//	LSHW rreg ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}
	SLL	R1, R2, R3

	//	LSHW rreg ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	SLL	R1, R2

	//	LSHW imm ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}

// MULL r1,r2,(hi,lo)
//
//	LTYPEM cond reg ',' reg ',' regreg
//	{
//		outcode($1, $2, &$3, int32($5.Reg), &$7);
//	}
	MULL	R1, R2, (R3,R4)

//
// MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4
// MULAW{T,B} r1,r2,r3,r4
//
//	LTYPEN cond reg ',' reg ',' reg ',' spreg
//	{
//		$7.Type = obj.TYPE_REGREG2;
//		$7.Offset = int64($9);
//		outcode($1, $2, &$3, int32($5.Reg), &$7);
//	}
	MULAWT	R1, R2, R3, R4

func Loong64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
	var ok bool
	var arngType int16
	var simdType int16
	var simdReg int16

	switch {
	case reg >= loong64.REG_V0 && reg <= loong64.REG_V31:
		simdType = loong64.LSX
		simdReg = reg - loong64.REG_V0
	case reg >= loong64.REG_X0 && reg <= loong64.REG_X31:
		simdType = loong64.LASX
		simdReg = reg - loong64.REG_X0
	default:

     *
     * @throws NullPointerException if {@code seg} is {@code null}.
     */
    @Nonnull
    public Path resolve(String seg) {
        requireNonNull(seg, "seg");
        return directory.resolve(seg).normalize();
    }

    /**
     * Changes current cwd, if the new path is existing directory.
     *
     * @throws NullPointerException if {@code seg} is {@code null}.

app.include_router(router, prefix="/{segment}")


client = TestClient(app)


def test_get():
    response = client.get("/seg/users/foo")
    assert response.status_code == 200, response.text

	// Expect (SB), (FP), (PC), or (SP)
	p.get('(')
	reg := p.get(scanner.Ident).String()
	p.get(')')
	p.setPseudoRegister(a, reg, isStatic, prefix)
}

// setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
	if addr.Reg != 0 {
		p.errorf("internal error: reg %s already set in pseudo", reg)
	}
	switch reg {

Joe Tsai <******@****.***> 1443691829 -0700

			// the CR bit.
			prog.Reg = a[1].Reg
			if a[1].Type != obj.TYPE_REG {
				// The CR bit is represented as a constant 0-31. Convert it to a Reg.
				c := p.getConstant(prog, op, &a[1])
				reg, success := ppc64.ConstantToCRbit(c)
				if !success {
					p.errorf("invalid CR bit register number %d", c)
				}
				prog.Reg = reg
			}
			break
		}

}

// ARM64RegisterShift constructs an ARM64 register with shift operation.
func ARM64RegisterShift(reg, op, count int16) (int64, error) {
	// the base register of shift operations must be general register.
	if reg > arm64.REG_R31 || reg < arm64.REG_R0 {
		return 0, errors.New("invalid register for shift operation")
	}
	return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
}