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Results 1 - 4 of 4 for ROTRconst (0.11 sec)

  1. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"},                    // arg0 right rotate by (arg1 mod 64) bits
    		{name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64"},   // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (SLLV x (MOVVconst [c])) => (SLLVconst x [c])
    (SRLV x (MOVVconst [c])) => (SRLVconst x [c])
    (SRAV x (MOVVconst [c])) => (SRAVconst x [c])
    (ROTR x (MOVVconst [c]))  => (ROTRconst x [c&31])
    (ROTRV x (MOVVconst [c])) => (ROTRVconst x [c&63])
    
    (SGT  (MOVVconst [c]) x) && is32Bit(c) => (SGTconst  [c] x)
    (SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
    
    // mul by constant
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		return true
    	}
    	return false
    }
    func rewriteValueLOONG64_OpLOONG64ROTR(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ROTR x (MOVVconst [c]))
    	// result: (ROTRconst x [c&31])
    	for {
    		x := v_0
    		if v_1.Op != OpLOONG64MOVVconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpLOONG64ROTRconst)
    		v.AuxInt = int64ToAuxInt(c & 31)
    		v.AddArg(x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
    			},
    		},
    	},
    	{
    		name:    "ROTRconst",
    		auxType: auxInt64,
    		argLen:  1,
    		asm:     loong64.AROTR,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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