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Results 1 - 10 of 35 for divlu (0.95 sec)
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src/cmd/internal/obj/loong64/anames.go
"SUBW", "DBAR", "SYSCALL", "TEQ", "TNE", "WORD", "XOR", "MASKEQZ", "MASKNEZ", "MOVV", "MOVVL", "MOVVR", "SLLV", "SRAV", "SRLV", "ROTRV", "DIVV", "DIVVU", "REMV", "REMVU", "MULV", "MULVU", "MULHV", "MULHVU", "ADDV", "ADDVU", "SUBV", "SUBVU", "TRUNCFV", "TRUNCDV", "TRUNCFW", "TRUNCDW", "MOVWU", "MOVFV",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
REMV R4, R5 // a5902200 REMV R4, R5, R6 // a6902200 REMVU R4, R5 // a5902300 REMVU R4, R5, R6 // a6902300 DIVV R4, R5 // a5102200 DIVV R4, R5, R6 // a6102200 DIVVU R4, R5 // a5102300 DIVVU R4, R5, R6 // a6102300 MOVH R4, result+16(FP) // 64604029 MOVH R4, 1(R5) // a4044029 MOVH y+8(FP), R4 // 64404028 MOVH 1(R5), R4 // a4044028 MOVHU R4, R5 // 8500cf00
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"CMP", "CMPU", "CMPEQB", "CNTLZW", "CNTLZWCC", "CRAND", "CRANDN", "CREQV", "CRNAND", "CRNOR", "CROR", "CRORN", "CRXOR", "DIVW", "DIVWCC", "DIVWVCC", "DIVWV", "DIVWU", "DIVWUCC", "DIVWUVCC", "DIVWUV", "MODUD", "MODUW", "MODSD", "MODSW", "EQV", "EQVCC", "EXTSB", "EXTSBCC", "EXTSH", "EXTSHCC", "FABS", "FABSCC", "FADD",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
DIVW R4, R5 // b90400b5b91d00a4b904005b DIVW R4, R5, R6 // b90400b5b91d00a4b904006b DIVDU R7, R8 // a7a90000b90400b8b98700a7b904008b DIVDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009b DIVWU R1, R2 // a7a90000b90400b2b99700a1b904002b DIVWU R1, R2, R3 // a7a90000b90400b2b99700a1b904003b MODD R1, R2 // b90400b2b90d00a1b904002a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Div64 x y) => (DIVV x y) (Div64u ...) => (DIVVU ...) (Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y)) (Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y)) (Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y)) (Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)) (Div(32|64)F ...) => (DIV(F|D) ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
test/codegen/arithmetic.go
func Pow2DivisibleSigned(n1, n2 int) (bool, bool) { // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"PAUSE", "ADDIW", "SLLIW", "SRLIW", "SRAIW", "ADDW", "SLLW", "SRLW", "SUBW", "SRAW", "LD", "SD", "MUL", "MULH", "MULHU", "MULHSU", "MULW", "DIV", "DIVU", "REM", "REMU", "DIVW", "DIVUW", "REMW", "REMUW", "LRD", "SCD", "LRW", "SCW", "AMOSWAPD", "AMOADDD", "AMOANDD", "AMOORD", "AMOXORD", "AMOMAXD", "AMOMAXUD",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/runtime/time_windows_386.s
SBBL $(delta >> 32), DX // nano/100 = DX:AX // split into two decimal halves by div 1e9. // (decimal point is two spots over from correct place, // but we avoid overflow in the high word.) MOVL $1000000000, CX DIVL CX MOVL AX, DI MOVL DX, SI // DI = nano/100/1e9 = nano/1e11 = sec/100, DX = SI = nano/100%1e9 // split DX into seconds and nanoseconds by div 1e7 magic multiply. MOVL DX, AX MOVL $1801439851, CX MULL CX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 07 17:19:45 UTC 2023 - 1.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Select1 (Mul64uhilo x y)) => (MULLD x y) (Div64 [false] x y) => (DIVD x y) (Div64u ...) => (DIVDU ...) (Div32 [false] x y) => (DIVW x y) (Div32u ...) => (DIVWU ...) (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y)) (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0)