package s390x

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADD",
	"ADDC",
	"ADDE",
	"ADDW",
	"DIVW",
	"DIVWU",
	"DIVD",
	"DIVDU",
	"MODW",
	"MODWU",
	"MODD",
	"MODDU",
	"MULLW",
	"MULLD",
	"MULHD",
	"MULHDU",
	"MLGR",
	"SUB",
	"SUBC",
	"SUBV",
	"SUBE",
	"SUBW",
	"NEG",
	"NEGW",
	"MOVWBR",
	"MOVB",
	"MOVBZ",
	"MOVH",
	"MOVHBR",
	"MOVHZ",

	MODD	R1, R2, R3            // b90400b2b90d00a1b904003a
	MODW	R4, R5                // b90400b5b91d00a4b904005a
	MODW	R4, R5, R6            // b90400b5b91d00a4b904006a
	MODDU	R7, R8                // a7a90000b90400b8b98700a7b904008a
	MODDU	R7, R8, R9            // a7a90000b90400b8b98700a7b904009a
	MODWU	R1, R2                // a7a90000b90400b2b99700a1b904002a
	MODWU	R1, R2, R3            // a7a90000b90400b2b99700a1b904003a

		{name: "MODW", argLength: 2, reg: gp21tmp, asm: "MODW", resultInArg0: true, clobberFlags: true}, // arg0 % arg1

		{name: "MODDU", argLength: 2, reg: gp21tmp, asm: "MODDU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1
		{name: "MODWU", argLength: 2, reg: gp21tmp, asm: "MODWU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1

(Hmul(64|64u) ...) => (MULH(D|DU) ...)
(Hmul32  x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y)))
(Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y)))

(Mod64 x y) => (MODD x y)
(Mod64u ...) => (MODDU ...)
// MODW/MODWU has a 64-bit dividend and a 32-bit divisor,
// so a sign/zero extension of the dividend is required.
(Mod32  x y) => (MODW  (MOVWreg x) y)
(Mod32u x y) => (MODWU (MOVWZreg x) y)

			},
			clobbers: 2048, // R11
			outputs: []outputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MODDU",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.AMODDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14