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Results 1 - 10 of 22 for SLL (0.02 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Lsh64x32 <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
    (Lsh64x64 <t> x y) && !shiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] y)))
    
    (Lsh8x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLL x y)
    (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLL x y)
    (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLL x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  2. src/internal/runtime/atomic/atomic_mipsx.s

    	MOVBU	val+4(FP), R2
    	MOVW	$~3, R3
    	AND	R1, R3
    #ifdef GOARCH_mips
    	// Big endian.  ptr = ptr ^ 3
    	XOR	$3, R1
    #endif
    	AND	$3, R1, R4	// R4 = ((ptr & 3) * 8)
    	SLL	$3, R4
    	MOVW	$0xFF, R5
    	SLL	R4, R2
    	SLL	R4, R5
    	NOR	R0, R5
    	OR	R5, R2	// Shift val for aligned ptr. R2 = val << R4 | ^(0xFF << R4)
    	SYNC
    try_and8:
    	LL	(R3), R4	// R4 = *R3
    	AND	R2, R4
    	SC	R4, (R3)	// *R3 = R4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 21:29:34 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  3. src/crypto/sha512/sha512block_riscv64.s

    	MOVBU	((index*8)+3)(X29), X8; \
    	SLL	$56, X5; \
    	SLL	$48, X6; \
    	OR	X5, X6, X5; \
    	SLL	$40, X7; \
    	OR	X5, X7, X5; \
    	SLL	$32, X8; \
    	OR	X5, X8, X5; \
    	MOVBU	((index*8)+4)(X29), X9; \
    	MOVBU	((index*8)+5)(X29), X6; \
    	MOVBU	((index*8)+6)(X29), X7; \
    	MOVBU	((index*8)+7)(X29), X8; \
    	SLL	$24, X9; \
    	OR	X5, X9, X5; \
    	SLL	$16, X6; \
    	OR	X5, X6, X5; \
    	SLL	$8, X7; \
    	OR	X5, X7, X5; \
    	OR	X5, X8, X5; \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 9.1K bytes
    - Viewed (0)
  4. test/codegen/rotate.go

    	z &= 15
    
    	// amd64:"ROLW",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x<<z | x>>(16-z)
    
    	// amd64:"RORW",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x>>z | x<<(16-z)
    
    	return a
    }
    
    func rot8nc(x uint8, z uint) uint8 {
    	var a uint8
    
    	z &= 7
    
    	// amd64:"ROLB",-"ANDQ"
    	// riscv64: "OR","SLL","SRL",-"AND\t"
    	a += x<<z | x>>(8-z)
    
    	// amd64:"RORB",-"ANDQ"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 6K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	SUB	R4, R5			// a5101100
    	SUBV	R4, R5			// a5901100
    	ADD	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  6. src/internal/runtime/atomic/atomic_riscv64.s

    	MOV	ptr+0(FP), A0
    	MOVBU	val+8(FP), A1
    	AND	$3, A0, A2
    	AND	$-4, A0
    	SLL	$3, A2
    	XOR	$255, A1
    	SLL	A2, A1
    	XOR	$-1, A1
    	AMOANDW A1, (A0), ZERO
    	RET
    
    // func Or8(ptr *uint8, val uint8)
    TEXT ·Or8(SB), NOSPLIT, $0-9
    	MOV	ptr+0(FP), A0
    	MOVBU	val+8(FP), A1
    	AND	$3, A0, A2
    	AND	$-4, A0
    	SLL	$3, A2
    	SLL	A2, A1
    	AMOORW	A1, (A0), ZERO
    	RET
    
    // func And(ptr *uint32, val uint32)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 7K bytes
    - Viewed (0)
  7. test/codegen/shift.go

    }
    
    // ------------------ //
    //   masked shifts    //
    // ------------------ //
    
    func lshMask64x64(v int64, s uint64) int64 {
    	// arm64:"LSL",-"AND"
    	// ppc64x:"RLDICL",-"ORN",-"ISEL"
    	// riscv64:"SLL",-"AND\t",-"SLTIU"
    	// s390x:-"RISBGZ",-"AND",-"LOCGR"
    	return v << (s & 63)
    }
    
    func rshMask64Ux64(v uint64, s uint64) uint64 {
    	// arm64:"LSR",-"AND",-"CSEL"
    	// ppc64x:"RLDICL",-"ORN",-"ISEL"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  8. istioctl/pkg/admin/istiodconfig.go

    	switch ga.outputFormat {
    	case "short":
    		w := new(tabwriter.Writer).Init(out, 0, 8, 3, ' ', 0)
    		_, _ = fmt.Fprintln(w, "ACTIVE SCOPE\tDESCRIPTION\tLOG LEVEL")
    		for _, sll := range resultScopeLogLevel {
    			_, _ = fmt.Fprintf(w, "%s\t%s\t%s\n", sll.ScopeName, sll.Description, sll.LogLevel)
    		}
    		return w.Flush()
    	case "json", "yaml":
    		outputBytes, err := json.MarshalIndent(&resultScopeLogLevel, "", "  ")
    Registered: Fri Jun 14 15:00:06 UTC 2024
    - Last Modified: Sat Apr 13 05:23:38 UTC 2024
    - 13.5K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/loong64/anames.go

    	"MULF",
    	"MULU",
    	"MULH",
    	"MULHU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"SC",
    	"SCV",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"ROTR",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/riscv64.s

    	AUIPC	$524287, X10				// 17f5ff7f
    
    	LUI	$0, X15					// b7070000
    	LUI	$167, X15				// b7770a00
    	LUI	$-524288, X15				// b7070080
    	LUI	$524287, X15				// b7f7ff7f
    
    	SLL	X6, X5, X7				// b3936200
    	SLL	X5, X6					// 33135300
    	SLL	$1, X5, X6				// 13931200
    	SLL	$1, X5					// 93921200
    	SRL	X6, X5, X7				// b3d36200
    	SRL	X5, X6					// 33535300
    	SRL	$1, X5, X6				// 13d31200
    	SRL	$1, X5					// 93d21200
    
    	SUB	X6, X5, X7				// b3836240
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
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