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Results 1 - 10 of 14 for SRA (0.02 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh16x16 <t> x y) && !shiftIsBounded(v) => (SRA  <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt16to64 y)))))
    (Rsh16x32 <t> x y) && !shiftIsBounded(v) => (SRA  <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt32to64 y)))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    	ROTR	R4, R5, R6		// a6101b00
    	SLLV	R4, R5			// a5901800
    	SLLV	R4, R5, R6		// a6901800
    	ROTRV	R4, R5			// a5901b00
    	ROTRV	R4, R5, R6		// a6901b00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  3. test/codegen/shift.go

    	// s390x:-"RISBGZ",-"AND",-"LOCGR"
    	return v >> (s & 63)
    }
    
    func rshMask64x64(v int64, s uint64) int64 {
    	// arm64:"ASR",-"AND",-"CSEL"
    	// ppc64x:"RLDICL",-"ORN",-"ISEL"
    	// riscv64:"SRA\t",-"OR",-"SLTIU"
    	// s390x:-"RISBGZ",-"AND",-"LOCGR"
    	return v >> (s & 63)
    }
    
    func lshMask32x64(v int32, s uint64) int32 {
    	// arm64:"LSL",-"AND"
    	// ppc64x:"ISEL",-"ORN"
    	// riscv64:"SLL",-"AND\t",-"SLTIU"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/riscv/anames.go

    	"SLTI",
    	"SLTIU",
    	"ANDI",
    	"ORI",
    	"XORI",
    	"SLLI",
    	"SRLI",
    	"SRAI",
    	"LUI",
    	"AUIPC",
    	"ADD",
    	"SLT",
    	"SLTU",
    	"AND",
    	"OR",
    	"XOR",
    	"SLL",
    	"SRL",
    	"SUB",
    	"SRA",
    	"JAL",
    	"JALR",
    	"BEQ",
    	"BNE",
    	"BLT",
    	"BLTU",
    	"BGE",
    	"BGEU",
    	"LW",
    	"LWU",
    	"LH",
    	"LHU",
    	"LB",
    	"LBU",
    	"SW",
    	"SH",
    	"SB",
    	"FENCE",
    	"FENCETSO",
    	"PAUSE",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/loong64/anames.go

    	"MULHU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"SC",
    	"SCV",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"ROTR",
    	"SUB",
    	"SUBD",
    	"SUBF",
    	"SUBU",
    	"SUBW",
    	"DBAR",
    	"SYSCALL",
    	"TEQ",
    	"TNE",
    	"WORD",
    	"XOR",
    	"MASKEQZ",
    	"MASKNEZ",
    	"MOVV",
    	"MOVVL",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/riscv64.s

    	SUB	X5, X6					// 33035340
    	SUB	$-2047, X5, X6				// 1383f27f
    	SUB	$2048, X5, X6				// 13830280
    	SUB	$-2047, X5				// 9382f27f
    	SUB	$2048, X5				// 93820280
    
    	SRA	X6, X5, X7				// b3d36240
    	SRA	X5, X6					// 33535340
    	SRA	$1, X5, X6				// 13d31240
    	SRA	$1, X5					// 93d21240
    
    	// 2.5: Control Transfer Instructions
    	JAL	X5, 2(PC)				// ef028000
    	JALR	X6, (X5)				// 67830200
    	JALR	X6, 4(X5)				// 67834200
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  7. test/codegen/arithmetic.go

    	// amd64:"SHRQ",-"IDIVQ"
    	// arm:"SRA",-".*udiv"
    	// arm64:"ASR",-"REM"
    	// ppc64x:"SRAD"
    	b := n2 % 64 // signed
    
    	return a, b
    }
    
    // Check that signed divisibility checks get converted to AND on low bits
    func Pow2DivisibleSigned(n1, n2 int) (bool, bool) {
    	// 386:"TESTL\t[$]63",-"DIVL",-"SHRL"
    	// amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ"
    	// arm:"AND\t[$]63",-".*udiv",-"SRA"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    // signed right shift
    (Rsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> x y)
    (Rsh32x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt32to64 x) y)
    (Rsh16x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt16to64 x) y)
    (Rsh8x(64|32|16|8)  <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt8to64 x) y)
    
    // unsigned right shift
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		v.reset(OpRISCV64SNEZ)
    		v.AddArg(x)
    		return true
    	}
    	return false
    }
    func rewriteValueRISCV64_OpRISCV64SRA(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (SRA x (MOVDconst [val]))
    	// result: (SRAI [int64(val&63)] x)
    	for {
    		x := v_0
    		if v_1.Op != OpRISCV64MOVDconst {
    			break
    		}
    		val := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpRISCV64SRAI)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "SLLW", argLength: 2, reg: gp21, asm: "SLLW"},                 // arg0 << (aux1 & 31), logical left shift of 32 bit value, sign extended to 64 bits
    		{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                   // arg0 >> (aux1 & 63), arithmetic right shift
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
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