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Results 1 - 10 of 24 for SRAW (0.04 sec)
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src/net/http/responsewrite_test.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 07 01:07:32 UTC 2022 - 6.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"LWU", "LH", "LHU", "LB", "LBU", "SW", "SH", "SB", "FENCE", "FENCETSO", "PAUSE", "ADDIW", "SLLIW", "SRLIW", "SRAIW", "ADDW", "SLLW", "SRLW", "SUBW", "SRAW", "LD", "SD", "MUL", "MULH", "MULHU", "MULHSU", "MULW", "DIV", "DIVU", "REM", "REMU", "DIVW", "DIVUW", "REMW", "REMUW", "LRD", "SCD", "LRW", "SCW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/net/http/requestwrite_test.go
t.Errorf("writing #%d, err = %q, want %q", i, g, e) continue } if err != nil { continue } if tt.WantWrite != "" { sraw := braw.String() if sraw != tt.WantWrite { t.Errorf("Test %d, expecting:\n%s\nGot:\n%s\n", i, tt.WantWrite, sraw) continue } } if tt.WantProxy != "" { setBody() var praw strings.Builder err = tt.Req.WriteProxy(&praw)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 07 01:07:32 UTC 2022 - 23.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
test/codegen/shift.go
return v >> (s & 31) } func rshMask32x64(v int32, s uint64) int32 { // arm64:"ASR",-"AND" // ppc64x:"ISEL",-"ORN" // riscv64:"SRAW","OR","SLTIU" // s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func rsh5Mask32x64(v int32, s uint64) int32 { // riscv64:"SRAW",-"OR",-"SLTIU" return v >> (s & 31) } func lshMask64x32(v int64, s uint32) int64 { // arm64:"LSL",-"AND"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
SRLW X5, X6, X7 // bb535300 SUBW X5, X6, X7 // bb035340 SRAW X5, X6, X7 // bb535340 ADDIW $1, X6 // 1b031300 SLLIW $1, X6 // 1b131300 SRLIW $1, X6 // 1b531300 SRAIW $1, X6 // 1b531340 ADDW X5, X7 // bb835300 SLLW X5, X7 // bb935300 SRLW X5, X7 // bbd35300 SUBW X5, X7 // bb835340 SRAW X5, X7 // bbd35340 ADDW $1, X6 // 1b031300 SLLW $1, X6 // 1b131300
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
"MOVDGE", "MOVDGT", "MOVDLE", "MOVDLT", "MOVDNE", "LOCR", "LOCGR", "FLOGR", "POPCNT", "AND", "ANDW", "OR", "ORW", "XOR", "XORW", "SLW", "SLD", "SRW", "SRAW", "SRD", "SRAD", "RLL", "RLLG", "RNSBG", "RXSBG", "ROSBG", "RNSBGT", "RXSBGT", "ROSBGT", "RISBG", "RISBGN", "RISBGZ", "RISBGNZ", "RISBHG", "RISBLG", "RISBHGZ",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y) (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y) (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVHreg x) y) (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVBreg x) y) // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. // result = shift >= 64 ? 0 : arg << shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/math/atanh_s390x.s
WORD $0xED305088 //sdb %f3,.L12-.L10(%r5) BYTE $0x00 BYTE $0x1B SUBW R4, R2 WFSDB V3, V2, V3 RISBGZ $32, $47, $0, R2, R1 SLD $32, R1, R1 LDGR R1, F2 WFMADB V4, V2, V16, V4 SRAW $8, R2, R1 WFMADB V4, V5, V6, V5 WFMDB V4, V4, V6 WFMADB V4, V1, V7, V1 WFMADB V2, V3, V4, V2 WFMADB V1, V6, V5, V1 FMOVD 56(R5), F3 FMOVD 48(R5), F5 WFMADB V4, V5, V3, V4
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 5.1K bytes - Viewed (0)