Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 30 for vdivsw (1.14 sec)

  1. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	VCTZDM V1, V2, V3                       // 106117c4
    	VDIVESD V1, V2, V3                      // 106113cb
    	VDIVESQ V1, V2, V3                      // 1061130b
    	VDIVESW V1, V2, V3                      // 1061138b
    	VDIVEUD V1, V2, V3                      // 106112cb
    	VDIVEUQ V1, V2, V3                      // 1061120b
    	VDIVEUW V1, V2, V3                      // 1061128b
    	VDIVSD V1, V2, V3                       // 106111cb
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 23 20:52:57 UTC 2023
    - 14.3K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/asm9_gtables.go

    	"VEXTDUBVLX",
    	"VEXTDDVRX",
    	"VEXTDDVLX",
    	"VEXPANDWM",
    	"VEXPANDQM",
    	"VEXPANDHM",
    	"VEXPANDDM",
    	"VEXPANDBM",
    	"VDIVUW",
    	"VDIVUQ",
    	"VDIVUD",
    	"VDIVSW",
    	"VDIVSQ",
    	"VDIVSD",
    	"VDIVEUW",
    	"VDIVEUQ",
    	"VDIVEUD",
    	"VDIVESW",
    	"VDIVESQ",
    	"VDIVESD",
    	"VCTZDM",
    	"VCNTMBW",
    	"VCNTMBH",
    	"VCNTMBD",
    	"VCNTMBB",
    	"VCMPUQ",
    	"VCMPSQ",
    	"VCMPGTUQCC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 16 20:18:50 UTC 2022
    - 42.6K bytes
    - Viewed (0)
  3. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	VCTZDM:         "vctzdm",
    	VDIVESD:        "vdivesd",
    	VDIVESQ:        "vdivesq",
    	VDIVESW:        "vdivesw",
    	VDIVEUD:        "vdiveud",
    	VDIVEUQ:        "vdiveuq",
    	VDIVEUW:        "vdiveuw",
    	VDIVSD:         "vdivsd",
    	VDIVSQ:         "vdivsq",
    	VDIVSW:         "vdivsw",
    	VDIVUD:         "vdivud",
    	VDIVUQ:         "vdivuq",
    	VDIVUW:         "vdivuw",
    	VEXPANDBM:      "vexpandbm",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/anames.go

    	"FCVTDS",
    	"FCVTHD",
    	"FCVTHS",
    	"FCVTSD",
    	"FCVTSH",
    	"FCVTZSD",
    	"FCVTZSDW",
    	"FCVTZSS",
    	"FCVTZSSW",
    	"FCVTZUD",
    	"FCVTZUDW",
    	"FCVTZUS",
    	"FCVTZUSW",
    	"FDIVD",
    	"FDIVS",
    	"FLDPD",
    	"FLDPQ",
    	"FLDPS",
    	"FMADDD",
    	"FMADDS",
    	"FMAXD",
    	"FMAXNMD",
    	"FMAXNMS",
    	"FMAXS",
    	"FMIND",
    	"FMINNMD",
    	"FMINNMS",
    	"FMINS",
    	"FMOVD",
    	"FMOVQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/avx512enc/avx512f.s

    	VDIVPD Z16, Z21, K3, Z14                           // 6231d5435ef0
    	VDIVPD Z9, Z21, K3, Z14                            // 6251d5435ef1
    	VDIVPD Z16, Z8, K3, Z14                            // 6231bd4b5ef0
    	VDIVPD Z9, Z8, K3, Z14                             // 6251bd4b5ef1
    	VDIVPD Z16, Z21, K3, Z15                           // 6231d5435ef8
    	VDIVPD Z9, Z21, K3, Z15                            // 6251d5435ef9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 410.5K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/x86/aenum.go

    	ACVTTSD2SL
    	ACVTTSD2SQ
    	ACVTTSS2SL
    	ACVTTSS2SQ
    	ACWD
    	ACWDE
    	ADAA
    	ADAS
    	ADECB
    	ADECL
    	ADECQ
    	ADECW
    	ADIVB
    	ADIVL
    	ADIVPD
    	ADIVPS
    	ADIVQ
    	ADIVSD
    	ADIVSS
    	ADIVW
    	ADPPD
    	ADPPS
    	AEMMS
    	AENTER
    	AEXTRACTPS
    	AF2XM1
    	AFABS
    	AFADDD
    	AFADDDP
    	AFADDF
    	AFADDL
    	AFADDW
    	AFBLD
    	AFBSTP
    	AFCHS
    	AFCLEX
    	AFCMOVB
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 16.3K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/x86/anames.go

    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  8. test/codegen/floats.go

    	return f * 2.0
    }
    
    func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    	// riscv64:"FMULD",-"FDIVD"
    	x := f1 / 16.0
    
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIVD"
    	// riscv64:"FMULD",-"FDIVD"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm/anames.go

    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    	"SWPW",
    	"RFE",
    	"SWI",
    	"MULA",
    	"MULS",
    	"MMULA",
    	"MMULS",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/riscv/anames.go

    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    	"AMOSWAPD",
    	"AMOADDD",
    	"AMOANDD",
    	"AMOORD",
    	"AMOXORD",
    	"AMOMAXD",
    	"AMOMAXUD",
    	"AMOMIND",
    	"AMOMINUD",
    	"AMOSWAPW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
Back to top