CALL ·asyncPreempt2(SB)
	FLDPD 472(RSP), (F30, F31)
	FLDPD 456(RSP), (F28, F29)
	FLDPD 440(RSP), (F26, F27)
	FLDPD 424(RSP), (F24, F25)
	FLDPD 408(RSP), (F22, F23)
	FLDPD 392(RSP), (F20, F21)
	FLDPD 376(RSP), (F18, F19)
	FLDPD 360(RSP), (F16, F17)
	FLDPD 344(RSP), (F14, F15)
	FLDPD 328(RSP), (F12, F13)
	FLDPD 312(RSP), (F10, F11)
	FLDPD 296(RSP), (F8, F9)
	FLDPD 280(RSP), (F6, F7)
	FLDPD 264(RSP), (F4, F5)

	FSTPD	(F10, F11), ((offset)+2*8)(RSP) \
	FSTPD	(F12, F13), ((offset)+4*8)(RSP) \
	FSTPD	(F14, F15), ((offset)+6*8)(RSP)

#define RESTORE_F8_TO_F15(offset) \
	FLDPD	((offset)+0*8)(RSP), (F8, F9) \
	FLDPD	((offset)+2*8)(RSP), (F10, F11) \
	FLDPD	((offset)+4*8)(RSP), (F12, F13) \

	FLDPD	-8(RSP), (F1, F2)   // e18b7f6d
	FLDPD	11(RSP), (F1, F2)   // fb2f0091610b406d
	FLDPD	1024(RSP), (F1, F2) // fb031091610b406d
	FLDPD.W	8(RSP), (F1, F2)    // e18bc06d
	FLDPD.P	8(RSP), (F1, F2)    // e18bc06c
	FLDPD	-31(R0), (F1, F2)   // 1b7c00d1610b406d
	FLDPD	-4(R0), (F1, F2)    // 1b1000d1610b406d
	FLDPD	-8(R0), (F1, F2)    // 01887f6d
	FLDPD	x(SB), (F1, F2)
	FLDPD	x+8(SB), (F1, F2)

	"FCVTHD",
	"FCVTHS",
	"FCVTSD",
	"FCVTSH",
	"FCVTZSD",
	"FCVTZSDW",
	"FCVTZSS",
	"FCVTZSSW",
	"FCVTZUD",
	"FCVTZUDW",
	"FCVTZUS",
	"FCVTZUSW",
	"FDIVD",
	"FDIVS",
	"FLDPD",
	"FLDPQ",
	"FLDPS",
	"FMADDD",
	"FMADDS",
	"FMAXD",
	"FMAXNMD",
	"FMAXNMS",
	"FMAXS",
	"FMIND",
	"FMINNMD",
	"FMINNMS",
	"FMINS",
	"FMOVD",
	"FMOVQ",
	"FMOVS",

	LDP	(10*8)(R20), (R10, R11)
	LDP	(12*8)(R20), (R12, R13)
	LDP	(14*8)(R20), (R14, R15)
	FLDPD	(16*8)(R20), (F0, F1)
	FLDPD	(18*8)(R20), (F2, F3)
	FLDPD	(20*8)(R20), (F4, F5)
	FLDPD	(22*8)(R20), (F6, F7)
	FLDPD	(24*8)(R20), (F8, F9)
	FLDPD	(26*8)(R20), (F10, F11)
	FLDPD	(28*8)(R20), (F12, F13)
	FLDPD	(30*8)(R20), (F14, F15)
	RET

// reflectcall: call a function with the given argument list

	FSTPQ	(R1, R2), (R0)                                   // ERROR "invalid register pair"
	FLDPD	(R0), (R1, R2)                                   // ERROR "invalid register pair"
	FLDPD	(R1), (F2, F2)                                   // ERROR "constrained unpredictable behavior"

		8)
	// TODO: FPCR? I don't think we'll change it, so no need to save.
	// Add floating point registers F0-F31.
	for i := 0; i < 31; i += 2 {
		reg := fmt.Sprintf("(F%d, F%d)", i, i+1)
		l.add2("FSTPD", "FLDPD", reg, 16)
	}
	if l.stack%16 != 0 {
		l.stack += 8 // SP needs 16-byte alignment
	}

	// allocate frame, save PC of interrupted instruction (in LR)
	p("MOVD R30, %d(RSP)", -l.stack)