MULSD   X0, X1
	ADDSD   exprodata<>+40(SB), X1
	MULSD   X0, X1
	ADDSD   exprodata<>+32(SB), X1
	MULSD   X0, X1
	ADDSD   exprodata<>+24(SB), X1
	MULSD   X0, X1
	ADDSD   exprodata<>+0(SB), X1
	MULSD   X0, X1
	ADDSD   exprodata<>+8(SB), X1
	MULSD   X1, X0
	MOVSD   exprodata<>+16(SB), X1
	ADDSD   X0, X1
	MULSD   X1, X0
	MOVSD   exprodata<>+16(SB), X1
	ADDSD   X0, X1
	MULSD   X1, X0

	MULSD   X5, X5 // x1= k, x2= f, x3= s, x4= s2, x5= s4
	// t1 := s2 * (L1 + s4*(L3+s4*(L5+s4*L7)))
	MOVSD   $L7, X6
	MULSD   X5, X6
	ADDSD   $L5, X6
	MULSD   X5, X6
	ADDSD   $L3, X6
	MULSD   X5, X6
	ADDSD   $L1, X6
	MULSD   X6, X4 // x1= k, x2= f, x3= s, x4= t1, x5= s4
	// t2 := s4 * (L2 + s4*(L4+s4*L6))
	MOVSD   $L6, X6
	MULSD   X5, X6
	ADDSD   $L4, X6
	MULSD   X5, X6
	ADDSD   $L2, X6

// --------------------- //

func Mul2(f float64) float64 {
	// 386/sse2:"ADDSD",-"MULSD"
	// amd64:"ADDSD",-"MULSD"
	// arm/7:"ADDD",-"MULD"
	// arm64:"FADDD",-"FMULD"
	// ppc64x:"FADD",-"FMUL"
	// riscv64:"FADDD",-"FMULD"
	return f * 2.0
}

func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
	// 386/sse2:"MULSD",-"DIVSD"
	// amd64:"MULSD",-"DIVSD"
	// arm/7:"MULD",-"DIVD"
	// arm64:"FMULD",-"FDIVD"

	// hypot = max * sqrt(1 + (min/max)**2)
	MOVQ    BX, X0
	MOVQ    CX, X1
	ORQ     CX, BX
	JEQ     isZero
	MOVAPD  X0, X2
	MAXSD   X1, X0
	MINSD   X2, X1
	DIVSD   X0, X1
	MULSD   X1, X1
	ADDSD   $1.0, X1
	SQRTSD  X1, X1
	MULSD   X1, X0
	MOVSD   X0, ret+16(FP)
	RET
isInfOrNaN:
	CMPQ    AX, BX
	JEQ     isInf
	CMPQ    AX, CX
	JEQ     isInf
	MOVQ    $NaN, AX
	MOVQ    AX, ret+16(FP) // return NaN
	RET

	"MOVDF",
	"MOVF",
	"MOVD",
	"CMPF",
	"CMPD",
	"ADDF",
	"ADDD",
	"SUBF",
	"SUBD",
	"MULF",
	"MULD",
	"NMULF",
	"NMULD",
	"MULAF",
	"MULAD",
	"NMULAF",
	"NMULAD",
	"MULSF",
	"MULSD",
	"NMULSF",
	"NMULSD",
	"FMULAF",
	"FMULAD",
	"FNMULAF",
	"FNMULAD",
	"FMULSF",
	"FMULSD",
	"FNMULSF",
	"FNMULSD",
	"DIVF",
	"DIVD",
	"SQRTF",
	"SQRTD",
	"ABSF",
	"ABSD",

	NMULF	F3, F7        // 437a27ee
	NMULD	F0, F1, F2    // 402b21ee
	NMULD	F3, F7        // 437b27ee
	MULAF	F5, F6, F7    // 057a06ee
	MULAD	F5, F6, F7    // 057b06ee
	MULSF	F5, F6, F7    // 457a06ee
	MULSD	F5, F6, F7    // 457b06ee
	NMULAF	F5, F6, F7    // 457a16ee
	NMULAD	F5, F6, F7    // 457b16ee
	NMULSF	F5, F6, F7    // 057a16ee
	NMULSD	F5, F6, F7    // 057b16ee
	FMULAF  F5, F6, F7    // 057aa6ee

	// See issue 36400.
	zero := 0.0
	// amd64:-"DIVSD"
	inf := 1 / zero // +inf. We can constant propagate this one.
	negone := -1.0

	// amd64:"DIVSD"
	z0 := zero / zero
	// amd64:"MULSD"
	z1 := zero * inf
	// amd64:"SQRTSD"
	z2 := math.Sqrt(negone)
	return z0 + z1 + z2
}

func nanGenerate32() float32 {
	zero := float32(0.0)
	// amd64:-"DIVSS"

	"MOVSWW",
	"MOVUPD",
	"MOVUPS",
	"MOVW",
	"MOVWLSX",
	"MOVWLZX",
	"MOVWQSX",
	"MOVWQZX",
	"MOVZWW",
	"MPSADBW",
	"MULB",
	"MULL",
	"MULPD",
	"MULPS",
	"MULQ",
	"MULSD",
	"MULSS",
	"MULW",
	"MULXL",
	"MULXQ",
	"MWAIT",
	"NEGB",
	"NEGL",
	"NEGQ",
	"NEGW",
	"NOPL",
	"NOPW",
	"NOTB",
	"NOTL",
	"NOTQ",
	"NOTW",
	"ORB",
	"ORL",

		{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul
		{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
		{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},                    // fp32 div

	{VMLA_EQ_F32, []int{2, 1, 0}, "VMLA", "MULAF"},
	{VMLA_EQ_F64, []int{2, 1, 0}, "VMLA", "MULAD"},
	{VMLS_EQ_F32, []int{2, 1, 0}, "VMLS", "MULSF"},
	{VMLS_EQ_F64, []int{2, 1, 0}, "VMLS", "MULSD"},
	{VNMLA_EQ_F32, []int{2, 1, 0}, "VNMLA", "NMULAF"},
	{VNMLA_EQ_F64, []int{2, 1, 0}, "VNMLA", "NMULAD"},
	{VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"},
	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},