z1 := zero * inf
	// amd64:"SQRTSD"
	z2 := math.Sqrt(negone)
	return z0 + z1 + z2
}

func nanGenerate32() float32 {
	zero := float32(0.0)
	// amd64:-"DIVSS"
	inf := 1 / zero // +inf. We can constant propagate this one.

	// amd64:"DIVSS"
	z0 := zero / zero
	// amd64:"MULSS"
	z1 := zero * inf
	return z0 + z1

	// arm64:`SMULH`,-`DIV`
	// arm:`MOVW`,`MUL`,-`.*udiv`
	b := n2 / 17 // signed

	return a, b
}

func FloatDivs(a []float32) float32 {
	// amd64:`DIVSS\s8\([A-Z]+\),\sX[0-9]+`
	// 386/sse2:`DIVSS\s8\([A-Z]+\),\sX[0-9]+`
	return a[1] / a[2]
}

func Pow2Mods(n1 uint, n2 int) (uint, int) {
	// 386:"ANDL\t[$]31",-"DIVL"
	// amd64:"ANDL\t[$]31",-"DIVQ"
	// arm:"AND\t[$]31",-".*udiv"

	"CVTTSS2SL",
	"CVTTSS2SQ",
	"CWD",
	"CWDE",
	"DAA",
	"DAS",
	"DECB",
	"DECL",
	"DECQ",
	"DECW",
	"DIVB",
	"DIVL",
	"DIVPD",
	"DIVPS",
	"DIVQ",
	"DIVSD",
	"DIVSS",
	"DIVW",
	"DPPD",
	"DPPS",
	"EMMS",
	"ENTER",
	"EXTRACTPS",
	"F2XM1",
	"FABS",
	"FADDD",
	"FADDDP",
	"FADDF",
	"FADDL",
	"FADDW",
	"FBLD",
	"FBSTP",
	"FCHS",

		{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul
		{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},                    // fp32 div
		{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true},                    // fp64 div

		{name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true},
		{name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true},
		{name: "DIVSS", argLength: 2, reg: fp21, asm: "DIVSS", resultInArg0: true},
		{name: "DIVSD", argLength: 2, reg: fp21, asm: "DIVSD", resultInArg0: true},

		// MOVSxload: floating-point loads
		// x==S for float32, x==D for float64

	d += b[i+1]
	// amd64: `SUBSS\t8\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), X[0-9]+`
	d -= b[i+2]
	// amd64: `MULSS\t12\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), X[0-9]+`
	d *= b[i+3]
	// amd64: `DIVSS\t16\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), X[0-9]+`
	d /= b[i+4]
	return c, d
}

func storeTest(a []bool, v int, i int) {
	// amd64: `BTL\t\$0,`,`SETCS\t4\([A-Z]+[0-9]*\)`
	a[4] = v&1 != 0

	DIVSD X11, X11                          // f2450f5edb
	DIVSS (BX), X2                          // f30f5e13
	DIVSS (R11), X2                         // f3410f5e13
	DIVSS X2, X2                            // f30f5ed2
	DIVSS X11, X2                           // f3410f5ed3
	DIVSS (BX), X11                         // f3440f5e1b
	DIVSS (R11), X11                        // f3450f5e1b
	DIVSS X2, X11                           // f3440f5eda

	DAA:             "DAA",
	DAS:             "DAS",
	DEC:             "DEC",
	DIV:             "DIV",
	DIVPD:           "DIVPD",
	DIVPS:           "DIVPS",
	DIVSD:           "DIVSD",
	DIVSS:           "DIVSS",
	DPPD:            "DPPD",
	DPPS:            "DPPS",
	EMMS:            "EMMS",
	ENTER:           "ENTER",
	EXTRACTPS:       "EXTRACTPS",
	F2XM1:           "F2XM1",
	FABS:            "FABS",

		v.AddArg3(val, base, mem)
		return true
	}
	return false
}
func rewriteValue386_Op386DIVSS(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
	// cond: canMergeLoadClobber(v, l, x) && clobber(l)
	// result: (DIVSSload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != Op386MOVSSload {
			break

				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "DIVSS",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ADIVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7